• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.12
• /
• pp.75-84
• /
• 2001

Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.7 s.349
• /
• pp.13-19
• /
• 2006

A 5Gb/s cross coupled transimpedance amplifier (TIA) & limiting amp(LA), regulated cascode(RGC) is realized in a 0.18$\mu$m CMOS technology for optical printed circuit board applications. The optical receiver demonstrates $92.8db{\Omega}$ transimpedance and limiting amplifier gain, 5Gb/s bandwidth for 0.5pF photodiode capacitance, and 9.74mW power dissipation from 1.8V, 2.4V supply. Input stage impedance is $50{\Omega}$. The circuit was implemented on an optical PCB, and the 5Gb/s data output signal was measured with a good data eye opening.

• Journal of electromagnetic engineering and science
• /
• v.4 no.4
• /
• pp.156-161
• /
• 2004

The MMIC cascode VCO is designed, fabricated, and measured for Ku-band Low Noise Blcok(LNB) system using InGaP/GaAs HBT technology. The phase noise of -116.4 dBc/Hz at 1 MHz offset with output power of 1.3 dBm is obtained at 11.526 GHz by applying 3 V and 11 mA, which is comparatively better characteristics than compared with the different configuration VCOs fabricated with other technologies. The simulated results of oscillation frequency and second harmonic suppression agree with the measured results. The phase noise is improved due to the use of the smallest value of inductor in frequency determining network and the InGaP ledge function of the technology. The chip size of $830\time781\;{\mu}m^2$ is also achieved.

• Journal of electromagnetic engineering and science
• /
• v.3 no.1
• /
• pp.1-6
• /
• 2003

In this paper, a sub-harmonic dual-gate FET mixer is suggested to improve the isolation characteristic between LO and RF ports of an unbalanced mixer. The mixer was designed by using single-gate FET cascode structure and driven by the second harmonic component of LO signal. A dual-gate FET mixer has good isolation characteristic since RF and LO signals are injected into gatel and gate2, respectively. In addition, the isolation characteristic of a sub-harmonic mixer is better than that of a fundamental mixer due to the large frequency separation between the LO and RF frequencies. As RF power was -30 ㏈m and LO power was 0 ㏈m, the designed mixer yielded the -47.17 ㏈m LO-to-RF leakage power level, 10 ㏈ conversion gain, -2.5 ㏈m OIP3, -12.5 ㏈m IIP3 and -1 ㏈m 1 ㏈ gain compression point. Since the LO-to-RF leakage power level of the designed mixer is as good as that of a double-balanced mixer, the sub-harmonic dual-gate FET mixer can be utilized instead.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.23 no.9
• /
• pp.667-670
• /
• 2010

In this paper, a high voltage current sensing circuit for boost converter is designed and verified by Cadence SPECTRE simulations. The current mirror pair, power and sensing metal-oxide semiconductor field effect transistors (MOSFETs) with size ratio of K, is used in our on-chip current sensing circuit. Very low drain voltages of the current mirror pair should be matched to give accurate current sensing, so a folded-cascode opamp with a PMOS input pair is used in our design. A high voltage high side lateral-diffused MOS transistor (LDMOST) switch is used between the current sensing circuit and power MOSFET to protect the current sensing circuit from the high output voltage. Simulation results using 0.35 ${\mu}m$ BCD process show that current sensing is accurate and the pulse frequency modulation (PFM) boost converter using the proposed current sensing circuit satisfies with the specifications.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
• /
• v.9 no.4
• /
• pp.141-146
• /
• 2010

In this paper, bandgap reference PTAT(Proportional to Absolute Temperature) circuit and flexible gain control of LNA(Low Noise Amplifier) which is usable in Zigbee system of 2.4GHz band are designed by TSMC $0.18{\mu}m$ CMOS library. PTAT bandgap reference circuit is proposed to minimize the instability of CMOS circuit which may be unstable in temperature changes. This circuit is designed such that output voltage remains within 1.3V even when the temperature varies from $-40^{\circ}C$ to $-50^{\circ}C$ when applied to the gate bias voltage of LNA. In addition, the LNA is designed to be operated on 2.4GHz which is applicable to Zigbee system and able to select gains by changing output impedance using 4 NMOS operated switches. The simulation result shows that achieved gain is 14.3~17.6dB and NF (Noise Figure) 1.008~1.032dB.

• Proceedings of the KIEE Conference
• /
• 2009.07a
• /
• pp.1597_1598
• /
• 2009

In this paper, the techniques and design focus of flexible gain coltrol of LAN(Low Noise Amplifier) using the TSMC 0.18um CMOS process. The design frequency set up a standard on 2.4GHz that is used in Zigbee system. The design concepts a basic Cascode LNA techniques and a swiching circuit consisted of 4 NMOS of load resistance, which convert the output impedenceby tuning on or off. The result show the gain change by NMOS operated swich. The simulation result is that Gain is 10.23~12.96dB and NF(Noise Figure) is 1.41~1.47dB.

• Journal of the Korea Computer Industry Society
• /
• v.2 no.10
• /
• pp.1253-1260
• /
• 2001

In this paper, a new voltage-controlled tunable analog active element for low-voltage applications and information protection is proposed. The proposed active element is composed of the CMOS complementary cascode circuit which can extend transconductance of an element. Therefore, the unity gain frequency which is determined transconductance is increased than that of the conventional element. And then these results are verified by the $0.25\mutextrm{m}$ CMOS n-well parameter HSPICE simulation. As a result, the gain and the unity gain frequency are 42㏈ and 200MHz respectively in the element on 2V supply voltage. And power dissipation of the designed circuit is 0.32mW.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.9-9
• /
• 2010

In this paper, High Brightness LED driver IC using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses $1{\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre(Cadence) simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.14-14
• /
• 2010

A high voltage current sensing circuit for LED driver IC is designed and verfied by Cadence SPECTRE simulations. The current mirror pair, power and sensing MOSFETs with size ratio of K, is used in our on-chip current sensing circuit. Very low drain voltages of the current mirror pair should be matched to give accurate current sensing, so a folded-cascode opamp with a PMOS input pair is used in our design. A high voltage high side LDMOST switch is used between the current sensing circuit and power MOSFET to protect the current sensing circuit from the high output voltage. Simulation results using 0.35um BCD process show that current sensing is accurate with properly frequency compensated opamp.