• 제목/요약/키워드: Cascaded multilevel inverter

검색결과 112건 처리시간 0.018초

Efficient Hybrid Carrier Based Space Vector Modulation for a Cascaded Multilevel Inverter

  • Govindaraju, C.;Baskaran, K.
    • Journal of Power Electronics
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    • 제10권3호
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    • pp.277-284
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    • 2010
  • This paper presents a novel hybrid carrier based space vector modulation for cascaded multilevel inverters. The proposed technique inherits the properties of carrier based space vector modulation and the fundamental frequency modulation strategy. The main characteristic of this modulation are the reduction of power loss, and improved harmonic performance. The carrier based space vector modulation algorithm is implemented with a TMS320F2407 digital signal processor. A Xilinx Complex Programmable Logic Device is used to develop the hybrid PWM control algorithm and it is integrated with a digital signal processor for hybrid carrier based space vector PWM generation. The inverter offers less weighted total harmonic distortion and it operates with equal electrostatic and electromagnetic stress among the power devices. The feasibility of the proposed technique is verified by spectral analysis, simulation, and experimental results.

A Generalized Space Vector Modulation Scheme Based on a Switch Matrix for Cascaded H-Bridge Multilevel Inverters

  • K.J., Pratheesh;G., Jagadanand;Ramchand, Rijil
    • Journal of Power Electronics
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    • 제18권2호
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    • pp.522-532
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    • 2018
  • The cascaded H Bridge (CHB) multilevel inverter (MLI) is popular among the classical MLI topologies due to its modularity and reliability. Although space vector modulation (SVM) is the most suitable modulation scheme for MLIs, it has not been used widely in industry due to the higher complexity involved in its implementation. In this paper, a simple and novel generalized SVM algorithm is proposed, which has both reduced time and space complexity. The proposed SVM involves the generalization of both the duty cycle calculation and switching sequence generation for any n-level inverter. In order to generate the gate pulses for an inverter, a generalized switch matrix (SM) for the CHB inverter is also introduced, which further simplifies the algorithm. The algorithm is tested and verified for three-phase, three-level and five-level CHB inverters in simulations and hardware implementation. A comparison of the proposed method with existing SVM schemes shows the superiority of the proposed scheme.

An Improved SPWM Strategy to Reduce Switching in Cascaded Multilevel Inverters

  • Dong, Xiucheng;Yu, Xiaomei;Yuan, Zhiwen;Xia, Yankun;Li, Yu
    • Journal of Power Electronics
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    • 제16권2호
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    • pp.490-497
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    • 2016
  • The analysis of the switch status of each unit module of a cascaded multi-level inverter reveals that the working condition of the switch of a chopper arm causes unnecessary switching under the conventional unipolar sinusoidal pulse width modulation (SPWM). With an increase in the number of cascaded multilevel inverters, the superposition of unnecessary switching gradually occurs. In this work, we propose an improved SPWM strategy to reduce switching in cascaded multilevel inverters. Specifically, we analyze the switch state of the switch tube of a chopper arm of an H-bridge unit. The redundant switch is then removed, thereby reducing the switching frequency. Unlike the conventional unipolar SPWM technique, the improved SPWM method greatly reduces switching without altering the output quality of inverters. The conventional unipolar SPWM technique and the proposed method are applied to a five-level inverter. Simulation results show the superiority of the proposed strategy. Finally, a prototype is built in the laboratory. Experimental results verify the correctness of the proposed modulation strategy.

Design of a Cascaded H-Bridge Multilevel Inverter Based on Power Electronics Building Blocks and Control for High Performance

  • Park, Young-Min;Ryu, Han-Seong;Lee, Hyun-Won;Jung, Myung-Gil;Lee, Se-Hyun
    • Journal of Power Electronics
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    • 제10권3호
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    • pp.262-269
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    • 2010
  • This paper proposes a practical design for a Cascaded H-Bridge Multilevel (CHBM) inverter based on Power Electronics Building Blocks (PEBB) and high performance control to improve current control and increase fault tolerance. It is shown that the expansion and modularization characteristics of the CHBM inverter are improved since the individual inverter modules operate more independently, when using the PEBB concept. It is also shown that the performance of current control can be improved with voltage delay compensation and the fault tolerance can be increased by using unbalance three-phase control. The proposed design and control methods are described in detail and the validity of the proposed system is verified experimentally in various industrial fields.

Modeling and Experimental Validation of 5-level Hybrid H-bridge Multilevel Inverter Fed DTC-IM Drive

  • Islam, Md. Didarul;Reza, C.M.F.S.;Mekhilef, Saad
    • Journal of Electrical Engineering and Technology
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    • 제10권2호
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    • pp.574-585
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    • 2015
  • This paper aims to improve the performance of conventional direct torque control (DTC) drives proposed by Takahashi by extending the idea for 5-level inverter. Hybrid cascaded H-bridge topology is used to achieve inverter voltage vector composed of 5-level of voltage. Although DTC is very popular for its simplicity but it suffers from some disadvantages like- high torque ripple and uncontrollable switching frequency. To compensate these shortcomings conventional DTC strategy is modified for five levels voltage source inverter (VSI). Multilevel hysteresis controller for both flux and torque is used. Optimal voltage vector selection from precise lookup table utilizing 12 sector, 9 torque level and 4 flux level is proposed to improve DTC performance. These voltage references are produced utilizing a hybrid cascaded H-bridge multilevel inverter, where inverter each phase can be realized using multiple dc source. Fuel cells, car batteries or ultra-capacitor are normally the choice of required dc source. Simulation results shows that the DTC drive performance is considerably improved in terms of lower torque and flux ripple and less THD. These have been experimentally evaluated and compared with the basic DTC developed by Takahashi.

A New Family of Cascaded Transformer Six Switches Sub-Multilevel Inverter with Several Advantages

  • Banaei, M.R.;Salary, E.
    • Journal of Electrical Engineering and Technology
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    • 제8권5호
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    • pp.1078-1085
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    • 2013
  • This paper presents a novel topology for cascaded transformer sub-multilevel converter. Eachsub-multilevel converter consists of two DC voltage sources with six switches to achieve five-level voltage. The proposed topology results in reduction of DC voltage sources and switches number. Single phase low frequency transformers are used in proposed topology and voltage transformation and galvanic isolation between load and sources are given by transformers. This topology can operate as symmetric or asymmetric converter but in this paper we have focused on symmetric state. The operation and performance of the suggested multilevel converter has been verified by the simulation results of a single-phase nine-level multilevel converter using MATLAB/SIMULINK.

3300V 1MVA H-브릿지 멀티레벨 인버터 개발 (Development of 3300V 1MVA Multilevel Inverter using Cascaded H-Bridge Cell)

  • 박영민;김연달;이현원;이세현;서광덕
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2003년도 춘계전력전자학술대회 논문집(2)
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    • pp.593-597
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    • 2003
  • Multilevel power conversion technology has received increasing attention recently for high power applications. The converters with the technology are suitable for high voltage and high power applications due to their ability to synthesize waveforms with better harmonic spectrum and apply for the high voltage equipment with a limited voltage rating of device. In the family of multilevel inverters, the topologies based on cascaded H-bridges are particularly attractive because of their modularity and simplicity of control. This paper presents multilevel inverter with cascaded H-bridge for large-power motor drives. The main features of this drive 1) reduce harmonic injection 2) can generate near-sinusoidal voltages, 3) have almost no common-mode voltage; 4) are low dv/dt at output voltage; 5)do not generate significant over-voltage on motor terminal; The topology of the developed product is presented and the feasibility study of the inverter on 3300v 1MVA 7-level H-bridge type was tarried out with experiments.

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Asymmetric Cascaded Multi-level Inverter: A Solution to Obtain High Number of Voltage Levels

  • Banaei, M.R.;Salary, E.
    • Journal of Electrical Engineering and Technology
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    • 제8권2호
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    • pp.316-325
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    • 2013
  • Multilevel inverters produce a staircase output voltage from DC voltage sources. Requiring great number of semiconductor switches is main disadvantage of multilevel inverters. The multilevel inverters can be divided in two groups: symmetric and asymmetric converters. The asymmetric multilevel inverters provide a large number of output steps without increasing the number of DC voltage sources and components. In this paper, a novel topology for multilevel converters is proposed using cascaded sub-multilevel Cells. This sub-multilevel converters can produce five levels of voltage. Four algorithms for determining the DC voltage sources magnitudes have been presented. Finally, in order to verify the theoretical issues, simulation is presented.

독립형 태양광 발전 시스템을 위한 새로운 19레벨 PWM 인버터 (A New 19-level PWM Inverter for the Use of Stand-alone Photovoltaic Power Generation Systems)

  • 강필순;오석규;박성준
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제53권7호
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    • pp.452-461
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    • 2004
  • A novel multilevel PWM inverter is presented for the use of stand-alone photovoltaic power generation system. In appearance, it consists of three full-bridge modules and three cascaded transformers; therefore, the configuration of the proposed multilevel PW inverter is equal to that of a prior 11-level PWM inverter. Only the turn-ratio of a transformer and its corresponding switching function are different from each other. Owing to these differences, the proposed 19-level PWM inverter has two promising advantages. First, output voltage levels increase almost twofold. Consequently, it can generate more sinusoidal output voltage waveform. Second, due to a revised switching pattern, it lightens power imposed on the transformer, which is used for compensating output voltages with chopped pulses between steps. The validity of the proposed inverter system is verified by computer-aided simulations and experimental results based on a 1 [kW] prototype. The performance of the proposed 19-level PWM inverter is compared with the Prior 11-level PWM inverter and other counterparts.

A New Cascaded Multilevel Inverter Topology with Voltage Sources Arranged in Matrix Structure

  • Thamizharasan, S.;Baskaran, J.;Ramkumar, S.
    • Journal of Electrical Engineering and Technology
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    • 제10권4호
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    • pp.1552-1557
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    • 2015
  • The paper unleashes a new idea to arrive at reduced switch count topological structures configured in the form of a matrix for a cascaded Multi level inverter (CMLI). The theory encircles to minimize the number of switches involved in the conduction path and there from acclaim reduced input current distortion, lower switching losses and electromagnetic interference. The focus extends to standardize the number of power devices required for reaching different levels of output voltage from the same architecture. It includes appropriate pulse width modulation (PWM) strategy to generate firing pulses and ensure the desired operation of the power modules. The investigative study carries with it MATLAB based simulation and experimental results obtained using suitable prototypes to illustrate the viability of the proposed concept. The promising nature of the performance projects a new dimension in the use of single phase MLIs for renewable energy related applications.