• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2013년도 전력전자학술대회 논문집
• /
• pp.433-434
• /
• 2013

본 논문에서는 절연타입의 Half-bridge 구조를 이용하여 입력단을 구성하고 출력단에 5레벨의 출력전압을 생성할 수 있는 새로운 구조의 멀티레벨 PWM 인버터를 제안한다. 기존의 Cascaded H-bridge 멀티레벨 인버터는 두 대의 H-Bridge 인버터 모듈을 직렬 결합하여 5레벨의 출력전압을 생성하는 방식이며, 제안하는 방식은 기존 멀티레벨 인버터의 기본 모듈인 H-bridge의 전원을 절연타입의 Half-bridge 구조를 이용하여 구성하고 스위칭 소자 1개와 다이오드 1개를 추가한 구조이다. 동일한 5레벨의 출력전압 생성 시 기존 방식은 2차 측에 8개의 스위칭 소자가 사용되는 반면 제안된 방식은 5개의 스위칭 소자와 1개의 다이오드가 사용되기 때문에 스위칭 손실 및 부피를 줄일 수 있으며 입력단과 출력단 사이의 절연으로 인한 시스템의 안정성을 확보할 수 있다. PSIM 기반의 컴퓨터 시뮬레이션을 통해 제안된 멀티레벨 인버터의 타당성을 검증한다.

• Journal of Power Electronics
• /
• 제17권5호
• /
• pp.1186-1194
• /
• 2017

This paper proposes an improved low frequency Selective Harmonic Mitigation-PWM (SHM-PWM) technique. The proposed method mitigates the low order harmonics of the output voltage up to the $50^{th}$ harmonic well and satisfies the grid codes EN 50160 and CIGRE-WG 36-05. Using a modified criterion for the switching angles, the range of the modulation index for non-linear SHM equations is improved, without increasing the switching frequency of the CHB converter. Due to the low switching frequency of the CHB converter, mitigating the harmonics of the converter up to the $50^{th}$ order and finding a wider modulation index range, the size and cost of the passive filters can be significantly reduced with the proposed technique. Therefore, the proposed technique is more efficient than the conventional SHM-PWM. To verify the effectiveness of the proposed method, a 7-level Cascaded H-bridge (CHB) converter is utilized for the study. Simulation and experimental results confirm the validity of the above claims.

• 한국철도학회논문집
• /
• 제9권6호
• /
• pp.761-765
• /
• 2006

At present, harmonic currents cause serious problems in power conversion system using the semiconductor switching device. Also some of the conversion system provokes harmonic currents against to the main power supply system and causes hindrances for the system. Main power impedance of the traditional LC passive filter method, influences on the filter characteristics and amplifies the harmonics when resonance phenomenon is occurred. And the traditional existing 2 level inverter systems show the limit in capacity of voltage and current in case of occurring sudden load change. So, to solve this problem active filter which uses cascaded H-bridge multi level inverter has been designed and ex-filter system circuits were totally investigated. With multi level active filtering system not only the size of filter but also the size of filter for transformer can be reduced by half and so as to the weight, while the capacity of inverter can be double sized and wave forms can be compensated exactly and precisely. Also by the benefit of the increase in rating capacity, the various currents owing to the load fluctuation can be dealt more steadily. In order to simulate the wave form of harmonics based on the measured data on the AC 25kV high speed Domestic Commercial railway, it was simulated with PSCAD/EMTDC and PSIM. Based on the results of this demonstration, the power supply system and inverter system would be more stable and also promoting its efficiency.

• Journal of Power Electronics
• /
• 제14권3호
• /
• pp.488-498
• /
• 2014

This paper presents an implementation of selective harmonic elimination (SHE) modulation for a single-phase 13-level transistor-clamped H-bridge (TCHB) based cascaded multilevel inverter. To determine the optimum switching angle of the SHE equations, the Newton-Raphson method is used in solving the transcendental equation describing the fundamental and harmonic components. The proposed SHE scheme used the relationship between the angles and a sinusoidal reference waveform based on voltage-angle equal criteria. The proposed SHE scheme is evaluated through simulation and experimental results. The digital modulator based-SHE scheme using a field-programmable gate array (FPGA) is described and has been implemented on an Altera DE2 board. The proposed SHE is efficient in eliminating the $3^{rd}$, $5^{th}$, $7^{th}$, $9^{th}$ and $11^{th}$ order harmonics, which validates the analytical results. From the results, it can be seen that the adopted 13-level inverter produces a higher quality with a better harmonic profile and sinusoidal shape of the stepped output waveform.

• Journal of Power Electronics
• /
• 제17권1호
• /
• pp.222-231
• /
• 2017

In this paper, a new architecture for a cost-effective power conditioning systems (PCS) using a single-sourced asymmetric cascaded H-bridge multilevel inverter (MLI) for photovoltaic (PV) applications is proposed. The asymmetric MLI topology has a reduced number of parts compared to the symmetrical type for the same number of voltage level. However, the modulation index threshold related to the drop in the number of levels of the inverter output is higher than that of the symmetrical MLI. This problem results in a modulation index limitation which is relatively higher than that of the symmetrical MLI. Hence, an extra voltage pre-regulator becomes a necessary component in the PCS under a wide operating bias variation. In addition to pre-stage voltage regulation for the constant MLI dc-links, another auxiliary pre-regulator should provide isolation and voltage balance among the multiple H-bridge cells in the asymmetrical MLI as well as the symmetrical ones. The proposed PCS uses a single-ended DC-DC converter topology with a coupled inductor and charge-pump circuit to satisfy all of the aforementioned requirements. Since the proposed integrated-type voltage pre-regulator circuit uses only a single MOSFET switch and a single magnetic component, the size and cost of the PCS is an optimal trade-off. In addition, the voltage balance between the separate H-bridge cells is automatically maintained by the number of turns in the coupled inductor transformer regardless of the duty cycle, which eliminates the need for an extra voltage regulator for the auxiliary H-bridge in MLIs. The voltage balance is also maintained under the discontinuous conduction mode (DCM). Thus, the PCS is also operational during light load conditions. The proposed architecture can apply the module-integrated converter (MIC) concept to perform distributed MPPT. The proposed architecture is analyzed and verified for a 7-level asymmetric MLI, using simulation results and a hardware implementation.

• Journal of Electrical Engineering and Technology
• /
• 제8권2호
• /
• pp.316-325
• /
• 2013

Multilevel inverters produce a staircase output voltage from DC voltage sources. Requiring great number of semiconductor switches is main disadvantage of multilevel inverters. The multilevel inverters can be divided in two groups: symmetric and asymmetric converters. The asymmetric multilevel inverters provide a large number of output steps without increasing the number of DC voltage sources and components. In this paper, a novel topology for multilevel converters is proposed using cascaded sub-multilevel Cells. This sub-multilevel converters can produce five levels of voltage. Four algorithms for determining the DC voltage sources magnitudes have been presented. Finally, in order to verify the theoretical issues, simulation is presented.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2017년도 전력전자학술대회
• /
• pp.70-71
• /
• 2017

This paper presents a new cascaded boost multilevel converter topology for distributed generation (DG) systems. Most of DG systems, such as photovoltaic (PV), wind turbine and fuel cells, normally require the complex structure power converters, which makes the system expensive, complex and hard to control. However, the proposed converter topology can generate a much higher output voltage just by using the standard low-voltage switch devices and low voltage DC-sources in a simplified structure, also enhancing the reliability of the switch devices. Simulation and experimental results with a 1.2kW system are presented to validate the proposed topology and control method.

• 전력전자학회논문지
• /
• 제16권3호
• /
• pp.283-292
• /
• 2011

본 논문에서는 기존의 멀티레벨 인버터와는 달리 DC링크단에 스위치를 설치함으로써 성능을 향상시킨 새로운 형태의 H-브리지 멀티레벨 인버터를 제안한다. 제안된 방식은 계통 연계형 단상 멀티레벨 인버터로서 기존의 단상인버터에 비하여 출력 전압 파형이 정현파에 가깝고, 고압 대용량 시스템용 멀티레벨 인버터로의 확장도 용이할 뿐만 아니라 직렬연결을 통하여 간단히 전압레벨을 확장할 수 있다는 장점을 갖는다. 동일한 5레벨의 경우 기존의 H-브리지 직렬형이나 NPC형 멀티레벨 인버터는 가제어 스위치가 8개 사용되는 반면에 제안한 멀티레벨 인버터는 가제어 스위치가 6개 사용되기 때문에 회로 구성이 간단하여 신뢰도가 높고 경제적인 구현이 가능하고 스위칭 손실이 줄어서 효율이 향상되는 특징이 있다. POD 변조기법을 기반으로 하여 반송파 신호 하나만을 사용하는 새로운 PWM 방법을 제시하였으며 DC링크 커패시터 전압의 균형을 위한 스위칭 시퀀스에 대해서도 검토하였다. 제안된 토폴로지의 타당성을 시뮬레이션과 실험을 통하여 확인하였다.

• KIEE International Transactions on Power Engineering
• /
• 제5A권1호
• /
• pp.22-30
• /
• 2005

The PWM inverter drive may cause an over voltage at the motor terminal, which imposes severe electric stresses on the inter-turn insulation of motor windings. Unlike low-voltage induction motors, high-voltage induction motors have a stator type of form-wound coil for insulation and are insulated to the slot and the coil. So, this paper presents a PWM 3-level inverter, H-Bridge cascaded 7-level inverter and High-voltage induction motor model. It then analyzes the voltage that generates at the input terminal of the high-voltage induction motor fed by each inverter. Also, in order to examine a factor that influences the switching surge voltage, this paper proposes the system equivalent model and performs the case studies using EMTP.

• 조명전기설비학회논문지
• /
• 제20권3호
• /
• pp.45-52
• /
• 2006

본 논문에서는 H-bridge cascaded 7-level 인버터로 구동되는 고압 유도전동기에서 발생하는 과도과전압 저감을 위한 LCR 필터의 효과를 분석하였다. 인버터에서 발생하는 스위칭 서지 전압은 유도전동기 입력단자에서 과도과전압을 발생시킨다. 이 과도과전압은 고압 유도 전동기의 고정자 권선에 심각한 전압스트레스를 주어 전동기 절연사고를 발생시키는 주요원인이다. 과도과전압의 영향은 저압유도 전동기 보다 고압 유도전동기에서 더욱더 심각하게 발생한다. 이러한 과도과전압을 저감하기 위한 방안으로 LCR 필터를 선택하였으며, 필터를 인버터 출력단자에 연결하여 과도과전압 스트레스와 링잉을 저감한 것을 전동기 단자에서 전압파형과 고조파 스펙트럼을 통하여 증명하였다. 시뮬레이션은 전자계과도해석 프로그램인 EMTP(Electromagnetic Transients Program)을 사용하였다.