• Journal of Power Electronics
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• v.18 no.1
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• pp.56-69
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• 2018

In this paper, an improved Space Vector Modulation (SVM) based fault tolerant operation on a nine-level Cascaded H-Bridge (CHB) inverter with an additional backup circuit is proposed. Any type of fault in a power converter may result in a power interruption and productivity loss. Three different faults on H-bridge modules in all three phases based on the SVM approach are investigated with diagrams. Any fault in an inverter phase creates an unbalanced output voltage, which can lead to instability in the system. An additional auxiliary unit is connected in series to the three phase cascaded H-bridge circuit. With the help of this and the redundant switching states in SVM, the CHB inverter produces a balanced output with low harmonic distortion. This ensures high DC bus utilization under numerous fault conditions in three phases, which improves the system reliability. Simulation results are presented on three phase nine-level inverter with the automatic fault detection algorithm in the MATLAB/SIMULINK software tool, and experimental results are presented with DSP on five-level inverter to validate the practicality of the proposed SVM fault tolerance strategy on a CHB inverter with an auxiliary circuit.

• Journal of Power Electronics
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• v.17 no.1
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• pp.56-66
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• 2017

Fast and accurate fault detection is the primary step and one of the most important tasks in fault tolerant converters. In this paper, a fast and simple method is proposed to detect and diagnosis the faulty cell in a cascaded H-bridge multilevel inverter under a short circuit fault. In this method, the reference voltage is calculated using switching control pulses and DC-Link voltages. The comparison result of the output voltage and the reference voltage is used in conjunction with active cell pulses to detect the faulty cell. To achieve this goal, the cell which is active when the Fault signal turns to "0" is detected as the faulty cell. Furthermore, consideration of generating the active cell pulses is completely described. Since the main advantage of this method is its simplicity, it can be easily implemented in a programmable digital device. Experimental results obtained with an 11-level inverter prototype confirm the effectiveness of the proposed fault detection technique. In addition, they show that the diagnosis method is unaffected by variations of the modulation index.

• Journal of Power Electronics
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• v.10 no.2
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• pp.155-164
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• 2010

This paper presents a voltage control algorithm for a hybrid multilevel inverter based on a staged-perception of the inverter voltage vector diagram. The algorithm is applied to control a three-stage eighteen-level hybrid inverter, which has been designed with a maximum number of symmetrical levels. The inverter has a two-level main stage built using a conventional six-switch inverter and medium- and low- voltage three-level stages constructed using cascaded H-bridge cells. The distinctive feature of the proposed algorithm is its ability to avoid the undesirable high switching frequency for high- and medium- voltage stages despite the fact that the inverter's dc sources voltages are selected to maximize the number of levels by state redundancy elimination. The high- and medium- voltage stages switching algorithms have been developed to assure fundamental switching frequency operation of the high voltage stage and not more than few times this frequency for the medium voltage stage. The low voltage stage is controlled using a SVPWM to achieve the reference voltage vector exactly and to set the order of the dominant harmonics. The inverter has been constructed and the control algorithm has been implemented. Test results show that the proposed algorithm achieves the desired features and all of the major hypotheses have been verified.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2139-2149
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• 2016

In this study, a new type of cascaded modular multilevel inverters (CMMLIs) is presented which is able to produce a considerable number of output voltage levels with a reasonable number of components. Accordingly, each series stage of the proposed CMMLI is comprised of two same basic units that are connected with each other through two unidirectional power switches without aiming any of the full H-bridge cells. In addition, since the potentiality for generating a higher number of output voltage levels in CMMLIs hinges on the magnitude of the dc voltage sources used in each series unit, in the rest of this paper, four different algorithms for determining an appropriate value for the dc sources' magnitude are also presented. In the following, a comprehensive topological analysis between some CMMLI structures reported in the literature and proposed structure along with several simulation and experimental results will be also given to validate the lucrative benefits and viability of the proposed topology.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.504-505
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• 2010

본 논문에서는 양방향 스위치를 가지는 기존의 5-레벨 인버터를 직렬 결합하여 보다 많은 출력 전압 레벨을 형성할 수 있는 멀티레벨 인버터 구조를 제안한다. 제안된 회로는 동일한 출력 전압 레벨 형성시 기존의 Cascaded H-bridge cell 방식보다 사용하는 스위칭 소자를 줄일 수 있어 시스템 크기, 비용, 전력 손실을 저감시킬 수 있는 장점을 가진다. 제안된 회로는 입력 전압원의 크기를 5의 배수로 구성함으로서 보다 많은 수의 레벨을 생성시킬 수 있는 특징을 가진다. 본 논문에서는 두 대의 5-레벨 인버터를 직렬 결합함으로써 25-레벨의 출력전압을 생성시킬 수 있는 인버터에 대한 특성을 분석하고 시뮬레이션과 실험을 통해 타당성을 검증한다.