• Journal of Power Electronics
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• 제13권2호
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• pp.296-303
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• 2013

This paper proposes a high efficiency three-phase cascaded phase shifted H-bridge multi-level inverter without DC/DC converters for grid-tied multi string photovoltaic (PV) applications. The cascaded H-bridge topology is suitable for PV applications since each PV module can act as a separate DC source for each cascaded H-bridge module. The proposed phase shifted H-bridge multi-level topology offers advantages such as operation at a lower switching frequency and a lower current ripple when compared to conventional two level topologies. It is also shown that low ripple sinusoidal current waveforms are generated with a unity power factor. The control algorithm permits the independent control of each DC link voltage with a maximum power point for each string of PV modules. The use of the controller area network (CAN) communication protocol for H-bridge multi-level inverters, along with localized PWM generation and PV voltage regulation are implemented. It is also shown that the expansion and modularization capabilities of the H-bridge modules are improved since the individual inverter modules operate more independently. The proposed topology is implemented for a three phase 240kW multi-level PV power conditioning system (PCS) which has 40kW H-bridge modules. The experimental results show that the proposed topology has good performance.

• Journal of Power Electronics
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• 제14권1호
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• pp.165-174
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• 2014

The cascaded H-Bridge Dynamic Voltage Restorer (DVR) is used for protecting high voltage and large capacity loads from voltage sags. The LC filter in the DVR is needed to eliminate switching ripples, which also provides an accurate tracking feature in a certain frequency range. Therefore, the parameter optimization of the LC filter is especially important. In this paper, the value range functions for the inductance and capacitance in LC filters are discussed. Then, parameter variations under different conditions of voltage sags and power factors are analyzed. In addition, an optimized design method is also proposed with the consideration of multiple impact factors. A detailed optimization procedure is presented, and its validity is demonstrated by simulation and experimental results. Both results show that the proposed method can improve the LC filter design for a cascaded H-Bridge DVR and enhance the performance of the whole system.

• 한국인터넷방송통신학회논문지
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• 제13권1호
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• pp.77-82
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• 2013

주기가 다른 격자들로 구성된 평면 DFB 도파로의 필터 특성들을 등가 전송선로 망을 사용하여 구현하였다. 대역 필터 특성과 공진 특성을 정확하게 분석하기 위하여 Floquet 이론과 Babinet 원리에 기초한 종방향 모드 전송선로 이론 (L-MTLT)을 제시하였다. 수치해석 결과, 본 논문에서 제시한 해석법은 주기가 다른 격자들로 구성된 DFB 도파로의 필터 특성들을 분석하기 위한 간단한 수치 해석적 알고리즘을 제공하였으며, DFB 필터의 대역폭과 사이드로브의 억압특성 각 영역에서의 격자개수와 격자 종횡비 (aspect ratio)에 민감하게 의존함을 보였다.

• 한국전자파학회논문지
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• 제15권7호
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• pp.644-652
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• 2004

본 논문에서는 급전면의 개방스터브와 접지면의 슬롯으로 구성되어 있는 초광대역의 저지대역을 갖는 저역통과 여파기 단위 구조를 캐스캐이드한 저역통과 여파기를 설계하였다. 초광대역의 저지대역을 갖는 저역통과 여파기 단위 구조는 급전면 개방 스터브에 의해 통과대역 특성을 결정하는 여파기 구조와 이러한 여파기의 dual 구조로 접지면 슬롯에 의해 통과대역 특성을 결정하는 여파기 구조가 있으며, 각각의 단위구조를 캐스캐이드함으로써 단일 여파기보다 더욱 향상된 저지대역과 skirt 특성을 얻을 수 있었다. 개방 스터브에 의해 통과대역 특성이 결정되는 구조와 dual 구조의 캐스캐이드 여파기는 각각 1.035㎓와 1.286㎓에서 -3㏈ 차단 주파수를 가지며 저지대역은 두 구조 모두 -20㏈ 기준으로 20㎓ 이상의 광대역을 이루었다.

• 전기학회논문지
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• 제67권7호
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• pp.846-853
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• 2018

In this paper, an improved model predictive control (MPC) method is proposed, which reduces the amount of calculations caused by the increased number of candidate voltage vectors with the increased voltage level in multi-level inverters. When the conventional MPC method is used for multi-level inverters, all candidate voltage vectors are considered to predict the next-step current value. However, in the case that the sampling time is short, increased voltage level makes it difficult to consider the all candidate voltage vectors. In this paper, the improved MPC method which can get a fast transient response is proposed with a small amount of the computation by adding new candidate voltage vectors that are set to find the optimal vector. As a result, the proposed method shows faster transient response than the method that considers the adjacent vectors and reduces the computational burden compared to the method that considers the whole voltage vector. the performance of the proposed method is verified through simulations and experiments.

• Journal of Electrical Engineering and Technology
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• 제12권6호
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• pp.2278-2288
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• 2017

Multilevel converter topologies are widely used in many applications. The cascaded H-bridge multilevel inverter (CHBMI), which is one of many multilevel converter topologies, has been introduced as a useful topology in high and medium power. However, it has a drawback to require a lot of switches. Therefore, the reliability of CHBMI is important factor for analyzing the performance. This paper presents a simple switch fault diagnosis method for single-phase CHBMI. There are two types of switch faults: open-fault and short-fault. In the open-fault, the body diode of faulty switch provides a freewheeling current path. However, when the short-fault occurs, the distortion of output current is different from that of the open-fault because it has an unavailable freewheeling current flow path due to a disconnection of fuse. The fault diagnosis method is based on the zero current time analysis according to zero-voltage switching states. Using the proposed method, it is possible to detect the location of faulty switch accurately. The PSIM simulation and experimental results show the effectiveness of proposed switch fault diagnosis method.

• Journal of Electrical Engineering and Technology
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• 제8권6호
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• pp.1328-1336
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• 2013

Nowadays multilevel inverters are developing generally due to reduced voltage stress on power switches and low total harmonic distortion (THD) in output voltage. However, for increasing the output voltage levels the number of circuit devices are increased and it results in increasing the cost of converter. In this paper, a novel multilevel inverter is proposed. The suggested topology uses less number of power switches and related gate drive circuits to generate the same level in output voltage with comparison to traditional cascaded multilevel inverter. With the proposed topology all levels in output voltage can be realized. As an illustration, a symmetric 13-level and asymmetric 29-level proposed inverters have been simulated and implemented. The total peak inverse (PIV) and power losses of presented inverter are calculated and compared with conventional cascaded multilevel inverter. The presented analyses show that the power losses in the suggested multilevel inverter are less than the traditional inverters. Presented simulation and experimental results demonstrate the feasibility and applicability of the proposed inverter to obtain the maximum number of levels with less number of switches.

• Journal of Power Electronics
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• 제15권6호
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• pp.1508-1516
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• 2015

A single phase H-bridge inverter is employed in conventional Inductive Power Transfer (IPT) systems as the primary side power supply. These systems may not be suitable for some high power applications, due to the constraints of the power electronic devices and the cost. A high-frequency cascaded multi-level inverter employed in IPT systems, which is suitable for high power applications, is presented in this paper. The Phase Shift Pulse Width Modulation (PS-PWM) method is proposed to realize power regulation and selective harmonic elimination. Explicit solutions against phase shift angle and pulse width are given according to the constraints of the selective harmonic elimination equation and the required voltage to avoid solving non-linear transcendental equations. The validity of the proposed control approach is verified by the experimental results obtained with a 2kW prototype system. This approach is expected to be useful for high power IPT applications, and the output power of each H-bridge unit is identical by the proposed approach.

• 전력전자학회논문지
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• 제19권2호
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• pp.157-163
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• 2014

This paper proposes a two-stage step-down buck and a tapped-inductor boost cascaded converter for high efficiency photovoltaic micro-inverter applications. The proposed inverter is a new structure to inject a rectified sinusoidal current into a low-frequency switching inverter for single-phase grid with unity power factor. To build a rectified-waveform of the output current. the converter employs both of a high efficiency step-up and a step-down converter in cascade. In step-down mode, tapped inductor(TI) boost converter stops and the buck converter operates alone. In boost mode, the TI converter operates with the halt of buck operation. The converter provides a rectified current to low frequency inverter, then the inverter converts the current into a unity power-factor sinusoidal waveform. By applying a TI, the converter can decrease the turn-on ratios of the main switch in TI boost converter even with an extreme step-up operation. The performance validation of the proposed design is confirmed by an experimental results of a 120W hardware prototype.

• Journal of Power Electronics
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• 제18권2호
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• pp.522-532
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• 2018

The cascaded H Bridge (CHB) multilevel inverter (MLI) is popular among the classical MLI topologies due to its modularity and reliability. Although space vector modulation (SVM) is the most suitable modulation scheme for MLIs, it has not been used widely in industry due to the higher complexity involved in its implementation. In this paper, a simple and novel generalized SVM algorithm is proposed, which has both reduced time and space complexity. The proposed SVM involves the generalization of both the duty cycle calculation and switching sequence generation for any n-level inverter. In order to generate the gate pulses for an inverter, a generalized switch matrix (SM) for the CHB inverter is also introduced, which further simplifies the algorithm. The algorithm is tested and verified for three-phase, three-level and five-level CHB inverters in simulations and hardware implementation. A comparison of the proposed method with existing SVM schemes shows the superiority of the proposed scheme.