• The Journal of Industrial Distribution & Business
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• v.11 no.10
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• pp.75-89
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• 2020

Purpose: The container terminal is an area that plays an important role in the country's import and export. As the volume of containers increased worldwide, competition between terminals became fiercer, and increasing the productivity of terminals became more important. Re-handling is a serious obstacle that lowers the productivity of terminal. There are two ways to reduce re-handling in the terminal yard. The first method is to load containers in terminal yards using effective carry-in algorithms that reduce re-handling. The second method is to carry out effective remarshalling. In this paper, the performance of various carry-in algorithms and various remarshalling algorithms are reviewed. Next, we try to find the most effective combination of carry-in algorithm and remarshalling algorithm. Research design, data and methodology: In this paper, we analyze the performance of the four carry-in algorithms, AP, MDF, LVF, RP and the four remarshalling algorithms, ASI, ASI+, ASO, ASO+. And after making all the combinations of carry-in algorithms and remarshalling algorithms, we compare their performance to find the best combination. To that end, many experiments are conducted with eight types of 100 bays through simulation. Results: The results of experiments showed that AP was effective among the carry-in algorithms and ASO+ was effective among remarshalling algorithms. In the case of the LVF algorithm, the effect of carrying in was bad, but it was found to be effective in finding remarshalling solution. And we could see that ASI+ and ASO+, algorithms that carry out remarshalling even if they fail to find remarshalling solution, are also more effective than ASI and ASO. And among the combinations of carry-in algorithms and remarshalling algorithms, we could see that the combination of AP algorithm and ASO+ algorithm was the most effective combination. Conclusion: We compared the performance of the carry-in algorithms and the remarshalling algorithms and the performance of their combination. Since the performance of the container yard has a significant effect on the performance of the entire container terminal, it is believed that the results of this experiment will be effective in improving the performance of the container terminal when carrying-in or when remarshalling.

• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2980-2988
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• 1998

This paper describes the design of asynchronous adders based on carry selection and carry bypass techniques. The designs are faster than existing asynchronous adders which are based on ripple carry technique. It is caused by reducing the carry transfer time by using carry selection and carry bypass techniques. Also, the design uses tree structure to reduce the completion sensing time. The proposed adders are designed with CMOS domino logic and experimented with HSPICE simulator. Experimental results show that the proposed adders can be faster about 50% in average cases than previous ripple carry adders.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.11
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• pp.491-494
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• 2006

In the adder design, reduction of the delay of the carry propagation or ripple is the most important consideration. Previously, it was introduced that, if a redundant number system is adopted, the carry propagation is completely eliminated, with which addition can be done in a constant time, without regarding to the count of the digits of numbers involved in addition. In this paper, a RBCD(Redundant Binary Coded Decimal) is adopted to code 0 to 11, and an efficient and economic carry-free BCD adder is designed.

• Journal of Sericultural and Entomological Science
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• v.18 no.2
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• pp.107-110
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• 1976

In silk reeling process the carry-over cocoons must be submerged in the reeling baths filled with reeling water and left until reopening the operation. Under the detention the carry-over cocoons are apt to decay without any antiseptic treatment. Thus an useful antiseptic for the cocoons is urgently needed, and various antseptic agents have been tested for their applicability to the process. However, such an useful agent has not been developed yet. Formalin has been the only chemical used for antisepticizing carry-over cocoons, although it has many defects as the antiseptic for the cocoons. In these circumstances, recently we newly prepared an antiseptic useful for preventing the carryover cocoons from decaying. We named the new antiseptic preparation "Swi-Se-Yo." The Korean term "Swi-Se-Yo" literally means "please take a rest". Through a series of experiments with Swi-Se-Yo we obtained the following results: 1) Swi-Se-Yo, in 0.05% aqueous solution, exerted a good antiseptic effect on the boiled Cocoons submerged in the reeling baths and the effect lasted for 45 hours. The duration of the effect is about two times longer than that of Formalin. 2) The percentage of cocoon reel ability of the carry-over cocoons treated with Swi-Se-Yo was 6% higher than that of Formalin and was equal to that of flowing cold water. 3) The percentage of raw silk yield of the carry-over cocoons treated with Swi-Se-Yo was almost equal to that of Formalin and to that of flowing cold water. 4) The quality of raw silk of the carry-over cocoons treated with Swi-Se-Yo is the same as that of flowing cold water. Besides the above favourable results, Swi-Se-Yo has many advantages as an antiseptic. Chemically it is very stable. Its antimicrobial action is very strong and the spectrum is very broad. It can be available in water-soluble powder and in small bulk. And it is not harmful to human and domestic animals. Considering these profitable properties of Swi-Se-Yo, it will have a good reputation as a carry-over cocoon antiseptic. (The chemical composition and manufacturing method of Swi-Se-Yo will be published in the near future.)

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.3C
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• pp.256-262
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• 2002

This paper presents a novel radix-4 modular multiplication algorithm based on the sign estimation technique (3). The sign estimation technique detects the sign of a number represented in the form of a carry-sum pair. It can be implemented with 5-bit carry look-ahead adder. The hardware speed of the cryptosystem is dependent on the performance modular multiplication of large numbers. Our algorithm requires only (n/2+3) clock cycle for n bit modulus in performing modular multiplication. Our algorithm out-performs existing algorithm in terms of required clock cycles by a half, It is efficient for modular exponentiation with large modulus used in RSA cryptosystem. Also, we use high-speed adder (7) instead of CPA (Carry Propagation Adder) for modular multiplication hardware performance in fecal stage of CSA (Carry Save Adder) output. We apply RL (Right-and-Left) binary method for modular exponentiation because the number of clock cycles required to complete the modular exponentiation takes n cycles. Thus, One 1024-bit RSA operation can be done after n(n/2+3) clock cycles.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.5
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• pp.241-249
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• 2003

Carry lookahead(CLA) circuitry of decimal adders is proposed aiming at delay reduction. The truncation error in calculation of monetary interests may accumulate yielding a substantial amount of errors. Binary Coded Decimal(BCD) additions. for example, eliminate the truncation error in a fractional representation of decimal numbers. The proposed BCD carry lookahead scheme is aiming at the speed improvements without any truncation errors in the addition of decimal fractions. The delay estimation of the BCD CLA is demonstrated with improved performance in addition. Further reduction in delay can be achieved introducing non-weighted number system such as the excess-3 code.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.787-794
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• 1999

This paper presents an ENMODL(enhances NORA MODL) circuit and implements a high-speed 32 bit CLA(carry lookahead adder) with the new dynamic logics. The proposed logic can reduce the area and the Propagation delay of carry because output inverters and a clocking PMOS of second stage can be omitted in two-stage MODL(multiple output domino logic) circuits. The 32-bit CLA is implemented with 0.8um double metal CMOS Process and the carry propagation delay of the adder is about 3.9 nS. The ENMODL circuits can improve the performance in the high-speed computing circuits depending on the degree of recurrence.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.44-48
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• 2008

According to increment of stage, the speed of changeable stage Carry-increment adder can be close to $O(\sqrt{2n})$ because the word length which is computed in stage can be lengthened by 1 bit. But the number of stage bits is increased, fan-out of carry which is inputted in stage is increased. So tile speed can be slow. This paper presents a new carry-increment adder design method to fix the number of fan-outs regardless of the number of stages. By layout simulation of 37-bit adder, the area can be Increased up to 40%, but speed improvement up to 75% can be achieved, by the proposed method, compared with a conventional method.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1991.10a
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• pp.86-91
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• 1991

A capability of performing the optical logic and arithmetic operations is followed by an effective encoding technique. In this paper, we proposed the color light encoding technique. By using this encoding technique, the space bandwidth product(SBP) is minimized in the output plane. In addition, we proposed the pre-operation pro-carry processing method that performs faster than the same time operation and carry processing method in optical computing. We proposed that the color liquid crystal device(CLCD) is used as the encoded color light input source.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.34-41
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• 2002

This paper describes a scalable implementation method of a word-based RSA cryptoprocessor using pseudo carry look-ahead adder The basic organization of the modular multiplier consists of two layers of carry-save adders (CSA) and a reduced carry generation and Propagation scheme called the pseudo carry look-ahead adder for the high-speed final addition. The proposed modular multiplier does not need complicated shift and alignment blocks to generate the next word at each clock cycle. Therefore, the proposed architecture reduces the hardware resources and speeds up the modular computation. We implemented a single-chip 1024-bit RSA cryptoprocessor based on the word-based modular multiplier with 256 datapaths in 0.5${\mu}{\textrm}{m}$ SOG technology after verifying the proposed architectures using FPGA with PCI bus.