• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2637-2639
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• 2002

This paper presents the design and implementation of a baseband Modem using DSP that supports a wireless LAN. It is implemented with DSP and D/A and A/D Converters in baseband and tested without using IF and RF modules. In this paper, we have used the matched filler and DLL(delay lock loop) for synchronization. And the matched filter and the carrier recovery are directly connected. Therefore, the proposed architecture is very simple and the operation of DSP becomes fast.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.4
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• pp.598-603
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• 1990

This study evaluates the performance of an optical receiver for binary phase shift keying (BPSK) signals in the presence of short noise originating from the photo diode and phase noise of the optical source. The case of using I.O. hybrid compare with the fiber optic hybrid to mix received optical signal and laser local oscillator signal. The impact of these noise is minimized if loop natural frequency and power split ratio between data and carrier recovery branch are choosen optimally. Then it is obtained that required laser linewidt to achieve a BER of 10**-9. The results are the same except theat in case of using the fiber optic hybrid the required optical power is twice as much as the I.O. hybrid.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.4
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• pp.18-26
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• 2001

In this paper, we propose an ATC(Automatic Transfer mode Controller) algorithm and an average-mode-change method for use in Gear shift PLL which can automatically change loop gain. The proposed ATC algorithm accurately detects proper timing or the mode change and has a very simpler structure - than the conventional lock detector algorithm often used in QPSK. And the proposed average mode change method can obtain low errors of estimated frequency offset by averaging the loop filter output of frequency component in shift register. These algorithms are also useful in designing ASIC, since these algorithms occupy small circuit area and are adaptable for high speed digital processing. We also present phase tracking performance of proposed Gear-shift PLL, which is composed of polarity decision PD, ATC and average mode change circuit, and analyze the results by examining constellation at each mode.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.991-997
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• 2004

In this paper, we propose the architecture of modem receiver to fabricate HomePNA 2.0 chip. HomePNA suffers from inferior channel because of bridge tap, the effect of amateur HAM band and so on. To transfer data over such channel, HomePNA 2.0 uses training sequence to equalize channel and uses FD-QAM optionally as modulation method. So modem receiver demodulate QAM based signal and needs optimum architecture that fully uses these transmission feature. As a result of research, we define 2 mode function of modem receiver depending on TX/RX state. In this paper, particularly, we show the algorithm of equalizer, carrier phase recovery and frame synchromzationblock and propose architecture that improve the performance of channel equalization and is stable in operation. In the end, we estimate the performance of proposed HomePNA2.0 modem receiver over HomePNA TEST LOOP using SPW program.