• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.5
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• pp.400-409
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• 2001

A new phase-shifted parallel-input/series-output(PISO) dual converter for tush-power step-up applications has been proposed. Since the proposed converter shows a low switch turn-off voltage stress, switching devices with low conduction loss can be employed in order to improve the power conversion efficiency. Moreover, it features a low output capacitor root-mean-square(RMS) current stress, low input current and output voltage ripple contents, and fast control-to-output dynamics compared to its PWM counterpart. In this paper, the operation of the proposed converter is analyzed in detail and its mathematical models and steady-state solutions are presented. A comparative analysis with the conventional PWM PISO dual converter is also provided. To confirm the operation, features, and validity of the Proposed converter, experimental results from an 800W, 24-350Vdc prototype are presented.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.6
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• pp.587-593
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• 2011

A new high power density and low cost Photovoltaic Power Conditioning System (PV PCS) with energy storage system is proposed. Its high power density and cost effectiveness can be achieved through the unification of the maximum power point tracker and battery charger/discharger. Despite of the reduced power stage, the proposed system can achieve the same performances of maximum power point tracking and battery charging/discharging as the conventional system. Moreover, the high voltage stress across the link-capacitor can be relieved through the series-connected link-capacitor with the battery. Therefore, a large number of series/parallel-connected link-capacitors can be reduced by 4-times. Especially, when the utility power failure happens, both photovoltaic and battery energies can be supplied to the load with only one power stage. Therefore, it features a simpler structure, less mass, lower cost, and fewer devices. Finally, to confirm the operation, validity, and features of the proposed system, theoretical analysis and experimental results from a single phase AC 220Vrms/1.5kW prototype are presented.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.1
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• pp.91-97
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• 2014

Recently, the LED(Light Emitting Diode) is expected to replace conventional lamps including incandescent, halogen and fluorescent lamps for some general illumination application, due to some obvious features such as high luminous efficiency, safety, long life, environment-friendly characteristics and so on. To drive the LED, a single stage PFC(Power Factor Correction) flyback converter has been adopted to satisfy the isolation, PFC and low cost. The conventional flyback LED driver has the serious disadvantage of high 120Hz output current ripple caused by the PFC operation. To overcome this drawback, a new PFC flyback with low 120Hz output current ripple is proposed in this paper. It is composed of 2 power stages, the DCM(Discontinuous Conduction Mode) flyback converter for PFC and BCM(Boundary Conduction Mode) boost converter for tightly regulated LED current. Since the link capacitor is located in the secondary side, its voltage stress is small. Moreover, since the driver is composed of 2 power stages, small output filter and link capacitor can be used. Especially, since the flyback is operated at DCM, the PFC can be automatically obtained and thus, an additional PFC IC is not necessary. Therefore, only one control IC for BCM boost converter is required. To confirm the validity of the proposed converter, theoretical analysis and experimental results from a prototype of 24W LED driver are presented.

• Journal of Power Electronics
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• v.4 no.3
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• pp.161-168
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• 2004

This paper presents a new circuit topology of high-frequency soft switching commutation boost type PWM chopper-fed DC-DC power converter with a loadside auxiliary passive resonant snubber. In the proposed boost type chopper-fed DC-DC power converter circuit operating under a principle of ZCS turn-on and ZVS turn-off commutation, the capacitor and inductor in the auxiliary passive resonant circuit works as the lossless resonant snubber. In addition to this, the voltage and current peak stresses of the power semiconductor devices as well as their di/dt or dv/dt dynamic stress can be effectively reduced by the single passive resonant snubber treated here. Moreover, it is proved that chopper-fed DC-DC power converter circuit topology with an auxiliary passive resonant snubber could solve some problems on the conventional boost type hard switching PWM chopper-fed DC-DC power converter. The simulation results of this converter are illustrated and discussed as compared with the experimental ones. The feasible effectiveness of this soft witching DC-DC power converter with a single passive resonant snubber is verified by the 5kW, 20kHz experimental breadboard set up to be built and tested for new energy utilization such as solar photovoltaic generators and fuel sell generators.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.8
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• pp.1055-1063
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• 2014

Power losses of a 1-stage DC-DC converter and 2-stage DC-DC converter are compared in this paper. A phase-shift full-bridge DC-DC converter is considered as 1-stage topology. This topology has disadvantages in the stress of rectifier diodes because of the resonance between the leakage inductor of the transformer and the junction capacitor of the rectifier diode. 2-stage topology is composed of an LLC resonant full-bridge DC-DC converter and buck converter. The LLC resonant full-bridge DC-DC converter does not need an RC snubber circuit of the rectifier diode. However, there is the drawback that the switching loss of the buck converter is large due to the hard switching operation. To reduce the switching loss of the buck converter, SiC MOSFET is used. This paper analyzes and compares power losses of two topologies considering temperature condition. The validity of the power loss analysis and calculation is verified by a PSIM simulation model.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.4
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• pp.897-902
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• 2018

The purpose of this study is to develop a bioinformatic diagnostic system that diagnoses the patient 's health condition by using the output waveform generated by applying the impulse voltage of 13Hz to 7 body parts based on DFM (Diagnose Fure Funktionelle Medizine) theory. It is expected that the data acquired by the diagnostic system will be served as a device for diagnosing the status of the body organ as well as the mesenchymal tissue through inductive reasoning based on artificial intelligence. In this paper, we will limit the system to acquire and manage bio-signals.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.6
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• pp.469-475
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• 2017

Using impedance matching techniques as a way to increase system power transferability in capacitive wireless power transmission has been widely investigated in conventional studies. However, these techniques tend to increase the circuit volume and thus counterbalance the advantage of the simplicity in the energy link structure. In this paper, a compact circuit topology with one leakage-enhanced transformer is proposed in order to minimize the circuit volume for the capacitive power transfer system. This topology achieves a reactive compensation, and the system quality factor value can be reduced by the turn ratio. As a result, this topology not only reduces the overall system volume but also minimizes the voltage stress of the link capacitor. An optimal design guideline for the leakage-enhanced transformer is also presented. The advantages of the proposed scheme over the conventional method in terms of power efficiency and circuit volume are revealed through an analytic comparison. The feasibility of applying the new topology is also verified by conducting 50 W hardware tests.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.127-127
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• 2011

전하 트랩형 비휘발성 메모리는 10년 이상의 데이터 보존 능력과 빠른 쓰기/지우기 속도가 요구 된다. 그러나 두 가지 특성은 터널 산화막의 두께에 따라 서로 trade off 관계를 갖는다. 즉, 두 가지 특성을 모두 만족 시키면서 scaling down 하기는 매우 힘들다. 이것의 해결책으로 적층된 유전막을 터널 산화막으로 사용하여 쓰기/지우기 속도와 데이터 보존 특성을 만족하는 Tunnel Barrier engineered Memory (TBM)이 있다. TBM은 가운데 장벽은 높고 기판과 전극쪽의 장벽이 낮은 crested barrier type이 있으며, 이와 반대로 가운데 장벽은 낮고 기판과 전극쪽의 장벽이 높은 VARIOT barrier type이 있다. 일반적으로 유전율과 밴드갭(band gap)의 관계는 유전율이 클수록 밴드갭이 작은 특성을 갖는다. 이러한 관계로 인해 일반적으로 crested type의 터널 산화막층은 high-k/low-k/high-k의 물질로 적층되며, VARIOT type은 low-k/high-k/low-k의 물질로 적층된다. 이 형태는 밴드갭이 다른 물질을 적층했을 때 전계에 따라 터널 장벽의 변화가 민감하여 전자의 장벽 투과율이 매우 빠르게 변화하는 특징을 갖는다. 결국 전계에 민감도 향상으로 쓰기/지우기 속도가 향상되며 적층된 유전막의 물리적 두께의 증가로 인해 데이터 보존 특성 또한 향상되는 장점을 갖는다. 본 연구에서는 SiO2/Al2O3 (2/3 nm)와 SiO2/HfAlO (2/3 nm)의 이중 터널 산화막을 증착 시킨 MIS capacitor를 제작한 후 터널 산화막에 전하가 트랩되는 것을 피하기 위하여 다양한 열처리 온도에 따른 current-voltage (I-V), capacitance-voltage (C-V), constant current stress (CCS) 특성을 평가하였다. 급속열처리 공정온도는 600, 700, 800, 900 ${^{\circ}C}$에서 진행하였으며, 낮은 누설전류, 터널링 전류의 증가, 전하의 트랩현상이 최소화되는 열처리 공정의 최적화 실험을 진행하였다.