• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.1-8
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• 2005

An area-efficient DC-DC voltage up-converter in a poly-Si TFT technology for system-on-glass is described which provides low-ripple output. The voltage up-converter is composed of charge-pumping circuit, comparator with threshold voltage mismatch compensation, oscillator, buffer, and delay circuit for multi-phase clock generation. The low ripple output is obtained by multi-phase clocking without increasing neither clock frequency nor filtering capacitor The measurement results have shown that the ripple on the output voltage with 4-phase clocking is 123mV, while Dickson and conventional cross-coupled charge pump has 590mV and 215mV voltage ripple, respectively, for $Rout=100k\Omega$, Cout-100pF, and fclk=1MHz. The filtering capacitor required for 50mV ripple voltage is 1029pF and 575pF for Dickson and conventional cross-coupled structure, for Iout=100uA, and fclk=1MHz, while the proposed multi-phase clocking DC-DC converter with 4-phase and 6-phase clocking requires only 290pF and 157pF, respectively. The efficiency of conventional and the multi-phase clocking DC-DC converter with 4-phase clocking is $65.7\%\;and\;65.3\%$, respectively, while Dickson charge pump has $59\%$ efficiency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.362-370
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• 2010

In this paper, a compact RF Front-end module for Wireless Fidelity(Wi-Fi) and Worldwide Interoperability for Microwave Access(WiMAX) applications is realized by low temperature co-fired ceramic(LTCC) technology. The RF Front-end module is composed of three LTCC band-pass filters, a Film Bulk Acoustic Resonator(FBAR) filter, fully embedded matching circuits, an SPDT switch for mode selection, an SPDT switch for Tx/Rx selection, and an SP4T switch for band selection. The parasitic elements of 0.2~0.3 pF are generated by the structure of stacking in the top pad pattern for DC block capacitor of SPDT switch for mode selection. These kinds of parasitic elements break the matching characteristic, and thus, the overall electrical performance of the module is degraded. In order to compensate it, we insert a parallel lumped-element inductor on capacitor pad pattern for DC block, so that we obtain the optimized performance of the RF Front-end module. The fabricated RF front-end module has 12 layers including three inner grounds and it occupies less than $6.0mm{\times}6.0mm{\times}0.728mm$.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.3
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• pp.49-53
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• 2001

Vortical etching experiments of ($SrBi_2Ta_2O_9$)/Si thin films have been performed by using the inductively coupled plasma reactive ion etching (ICP-ME) apparatus. The purposes of these experiments are to get the effective area of vertical surface. Because this technology is very important to get good qualities of ferroelectric gate structure, capacitor and the minimum parasitic effects related to the excellent performances of the FRAM (Ferroelectric Random Access Memory) device. The reacting gases were Ar and $Cl_2$gases, and various $Ar/C1_2$flow ratios were used. The etching experiments were carried out at various RF powers such as 700, 700, 500W and at various DC powers such as 200, 150, 100, 50W, respectively. The maximum etch rate of $SrBi_2Ta_2O_9$/Si thin films was 1050 A/min at the $Ar/C1_2$ gas ratio of 20/16, RF power of 700 W and DC power of 200 W. From the SEM (scanning electron microscopy) image of the SBT thin films, the wall angle was as good as about $82^{\circ}$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.9
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• pp.6247-6253
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• 2015

This paper presents the transient-response improved LDO regulator based on parallel error amplifiers. The proposed LDO regulator consists of an error amplifier (E/A1) which has a high gain and narrow bandwidth and a second amplifier (E/A2) which has low gain and wide bandwidth. These amplifiers are in parallel structure. Also, to improve the transient-response properties and slew-rate, some circuit block is added. Using pole-splitting technique, an external capacitor is reduced in a small on-chip size which is suitable for mobile devices. The proposed LDO has been designed and simulated using a Megna/Hynix $0.18{\mu}m$ CMOS parameters. Chip layout size is $500{\mu}m{\times}150{\mu}m$. Simulation results show 2.5 V output voltage and 100 mA load current in an input condition of 2.7 V ~ 3.3 V. Regulation Characteristic presents voltage variation of 26.1 mV and settling time of 510 ns from 100mA to 0 mA. Also, the proposed circuit has been shown voltage variation of 42.8 mV and settling time of 408 ns from 0 mA to 100 mA.

• Korean Journal of Materials Research
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• v.2 no.5
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• pp.353-359
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• 1992

Thermal oxidation and plasma enhanced chemical vapor deposition of tantalum oxide thin films on p-type (100) Si substrates were studied to examine the dielectric nature of T$a_2O_5$ as a Al/T$a_2O_5$/p-Si capacitor. Microstructure and dielectric properties of the capacitors were investigated by XRD, AES, high frequency C-V analyzer, I-V meter and TEM. XRD analysis showed that the structure of T$a_2O_5$ films were amorphous, but the films were crystallized to hexagonal $\delta$-T$a_2O_5$ by 65$0^{\circ}C$ thermal oxidation treatment. It was found that the stoichiometry of the films was more or less close to 2 : 5. Leakage current density and relative dielectric constant of thermal oxidation T$a_2O_5$ film at 60$0^{\circ}C$ was 5.0${ imes}10^{-6}$/A/c$m^2 and 31.5, respectively. In the case of PECVD T$a_2O_5$film deposited at 0.47W/c$m^2 they were 2.5${ imes}10^{-5}$/A/$ extrm{cm}^2$ and 24.0, respectively. The morphology of the films and interfaces were investigated by TEM.

• Journal of the Korean Society of Safety
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• v.35 no.1
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• pp.1-11
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• 2020

Article 325 (Prevention of Fire Explosion due to Electrostatic) of the Rule for Occupational Safety and Health Standard specifies that in order to prevent the risk of disasters caused by static electricity, fire, explosion and static electricity in the production process, However, in order to do this, it is absolutely necessary to use a pre-detection technology and a detector for antistatic discharge prediction, which is a precautionary measure by static electricity in a fire / explosion hazard place, but in Korea, And there is no technical standard for the application of the technology of the explosion proof structure of the related equipment. Research methods include domestic and overseas electrostatic discharge detection technology and literature investigation of related equipment explosion proofing technology, domestic and foreign electrostatic discharge detection device production and use situation investigation, advanced foreign technology data analysis and benchmarking. In particular, we sought to verify the results of empirical experiments using electrostatic discharge detection technology through sample purchase and analysis of related major products, development of optimization technology through prototype production, evaluation, and supplementation, and expert knowledge through expert consultation. The results of this study were developed and fabricated two prototypes of electrostatic discharge detector based on the technology / standard related to electrostatic discharge detection technology in Korea and abroad through development of electrostatic discharge detection technology and development and production of detector. In addition, based on the development of electrostatic discharge detection technology, we developed an intrinsic safety explosion proof ib class explosion proof technology applicable to the process of using and handling flammable gas and flammable liquid vapor and combustible dust. In the case of the over voltage and minimum voltage are supplied to the explosion-proof structure ESD detector, check the state of the circuit and the transient and transient currents generated by the coil and capacitor elements during the input and standby of the signal pulse voltage. Explosion-proof equipment-Part 11: Intrinsically safe explosion proof structure The comparative evaluation with the reference curve in Annex A of "i" confirms that the characteristics of the intrinsically safe explosion protection structure are met.

• Journal of IKEEE
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• v.23 no.1
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• pp.14-21
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• 2019

In this paper, we implemented an on-board miniaturization antenna operating 2.4 GHz using MZR(Mu Zero Resonator). It is must be operating under the constraint that the size of the small terminal PCB should be $78{\times}38{\times}0.8mm^3$ and the size of the system should be $63{\times}38{\times}0.8mm^3$ and the size of the radiating part should be $15{\times}38{\times}0.8mm^3$. The feeding structure uses a CPW structure for stable feeding and a feeding point at the upper left of the system board. A magnetic field coupling structure is used for coupling the feeding part and the antenna. The resonance frequency of the MZR is determined by the series inductance and capacitance of the cell, so the gap between the cells, the length of the cell, the length of the interdigital capacitor, and the spacing between the radiation part and the ground plane are analyzed. The antenna was designed and fabricated using the results. The total size of the antenna including the feed structure is $20.8{\times}9.0{\times}0.8mm^3$, and the electrical length is $0.1664{\lambda}_0{\times}0.072{\lambda}_0{\times}0.0064{\lambda}_0$. The measurement result for 10 dB bandwidth, gain and directivity are 440 MHz(18.3%), 0.4405 dB, and 2.722 dB respectively. It is confirmed that the radiation pattern has omnidirectional characteristics and it can be applied to ultra small terminal antenna.

• Korean Chemical Engineering Research
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• v.55 no.2
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• pp.242-246
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• 2017

The application of composite cathode materials including $LiFePO_4$ (lithium iron phosphate) of olivine crystal structure, which has high thermal stability, were investigated as alternatives for hybrid battery-capacitors with a $LiMn_2O_4$ (spinel crystal structure) cathode, which exhibits decreased performance at high temperatures due to Mn-dissolution. However, these composite cathode materials have been shown to have a reduction in capacity by conducting life cycle experiments in which a $LiFePO_4$/activated carbon cell was charged and discharged between 1.0 V and 2.3 V at two temperatures, $25^{\circ}C$ and $60^{\circ}C$, which caused a degradation of the anode due to the lowered voltage in the anode. To avoid the degradation of the anode, composite cathodes of $LiFePO_4/LiMn_2O_4$ (50:50 wt%), $LiFePO_4$/activated carbon (50:50 wt%) and $LiNi_{1/3}Co_{1/3}Mn_{1/3}O_2$ (50:50 wt%) were prepared and the life cycle experiments were conducted on these cells. The composite cathode including $LiNi_{1/3}Co_{1/3}Mn_{1/3}O_2$ of layered crystal structure showed stable voltage behavior. The discharge capacity retention ratio of $LiNi_{1/3}Co_{1/3}Mn_{1/3}O_2$ was about twice as high as that of a $LiFePO_4/LiMn_2O_4$ cell at thermal stability experiment for a duration of 1,000 hours charged at 2.3 V and a temperature of $80^{\circ}C$.

• Applied Chemistry for Engineering
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• v.19 no.4
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• pp.407-412
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• 2008

As an activation procedure, in this study, the oxidation treatment of needle cokes with a dilute nitric acid and sodium chlorate $(NaClO_3)$, combined with heat treatment, was attempted. The structures of acid-treated and pyrolyzed coke were examined with XRD, FESEM, elemental analyzer, BET, and Raman spectroscopy. The behavior of double layer capacitance was investigated with the analysis of charge and discharge. The structure of needle coke treated with acid was revealed to a single phase of (001) diffraction peak after 24 h. On the other hand, thecoke oxidized by heat treatment was reduced to a graphite structure of (002) at $300^{\circ}C$. The distorted graphene layer structure, derived from the process of oxidation and reduction of the inter-layer, makes the pores by the electric field activation at the first charge, and generates the double layer capacitance from the second charge. The cell using pyrolyzed coke with 24 h acid treatment and $300^{\circ}C$ heat treatment exhibited the maximum capacitance per weight and volume of 33 F/g and 30 F/mL at the two-electrode system in the potential range of 0~2.5 V.

• Journal of IKEEE
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• v.13 no.1
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• pp.41-48
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• 2009

This paper describes an implementation of the analog front end (AFE) incorporated with the image signal processing (ISP) unit in the SoC, dominating the performance of the CCD image sensor system. New schemes are exploited in the high-frequency sampling to reduce the sampling uncertainty apparently as the frequency increases, in the structure for the wide-range variable gain amplifier (VGA) capable of $0{\sim}36\;dB$ exponential gain control to meet the needed bandwidth and accuracy by adopting a new parasitic insensitive capacitor array. Moreover, the double cancellation of the black-level noise was efficiently achieved both in the analog and the digital domain. The proposed topology fabricated in a $0.35-{\mu}m$ CMOS process was proved in a full CCD camera system of 10-bit accuracy, dissipating 80 mA at 15 MHz with a 3.3 V supply voltage.