• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
• /
• pp.80-83
• /
• 2000

The post-annealing treatments on rf magnetron sputtered PZT($Pb_{1.05}(Zr_{0.52},\;Ti_{0.48})O_3$) thin films($4000{\AA}$) have been investigated for a structure of PZT/Pt/Ti/Coming glass(1737). Crystallization properties of PZT films were strongly dependent on RTA(Rapid Thermal Annealing) annealing temperature and time. We were able to obtain a perovskite structure of PZT at $650^{\circ}C$ and 10min. P-E curves of Pd/PZT/Pt capacitor demonstrate typical hysteresis loops. The measured values of $P_r$, $E_c$ were $8.1[{\mu}C/cm^2]$, 95[kV/cm] respectively. Polarization value decrease about 25% after $10^9$ cycles.

• 한국정보전자통신기술학회논문지
• /
• 제2권4호
• /
• pp.59-64
• /
• 2009

본 논문에서는 새로운 형태의 도넛형 결함 접지면 구조를 이용한 공진기의 동작특성과 등가회로을 나타내고, 이것의 접지면에 칩 캐패시터를 추가하여 공진주파수를 가변할 수 있도록 설계하였다. 일반적으로 결함접지면 구조는 병렬 공진 특성을 갖는다. 여기에 집중소자 캐패시터를 추가하면 공진주파수가 낮아지게 된다. 캐패시터 대신에 바랙터다이오드를 이용하면 전압으로써 공진 주파수를 제어할 수 있다. 본 공진기는 전압제어발진기와 가변주파수 대역통과 여파기등에 응용될 수 있다.

• ETRI Journal
• /
• 제38권5호
• /
• pp.879-884
• /
• 2016

In this paper, an ultra-small marker beacon antenna operated in the VHF-band is proposed. This antenna has a modified linear IFA structure with a lumped capacitor and a capacitive plate for frequency tuning and impedance matching. The capacitive plate is directly connected to the end of a linear radiator and is separated from the antenna ground by 1 mm. The main operating frequency is mainly controlled by the size and dielectric constant of the capacitive plate. The lumped capacitor is useful for fine frequency tuning. Using the proposed structure, an ultra-small marker beacon antenna can be realized with a length of 0.04 ${\lambda}_0$.

• 한국결정성장학회지
• /
• 제14권3호
• /
• pp.90-94
• /
• 2004

The variation of electrical properties of (Ba,Sr)$TiO_3$ [BST] thin films for Metal-Insulator-Semiconductor (MIS) capacitors was investigated. BST thin films were deposited on p-Si(100) substrates by the RF magnetron sputtering with temperature range of 500~$600^{\circ}C$. The dielectric properties of MIS capacitors consisting of AUBST/$SiO_2$/Si sandwich structure were measured for various conditions. We examined the characteristics of MIS capacitor with various oxygen pressure, substrate temperature and (Ba+Sr)/Ti ratio. It was found that the leakage current was reduced in MIS capacitor with high quality $SiO_2$ layer was grown on bare p-Si substrate by thermal oxidation. The BST MIS structure showed relatively high capacitance even though it is the combination of high-dielectric BST thin films and $SiO_2$ layer. The charge state densities of the MIS capacitors and Current-voltage characteristics of the MIS capacitor were investigated. By applying $SiO_2$ layer between BST thin films and Si substrate, low leakage current of $10^{-10}$ order was observed.

• 공업화학
• /
• 제20권4호
• /
• pp.396-401
• /
• 2009

전기이중층 캐패시터의 성능향상을 위한 전극물질로서 resorcinol-formaldehyde수지를 탄소원으로 사용하여 meso-pore 비율 52~64%의 기공특성을 지니며 직경 $2{\sim}10{\mu}m$의 미세구형 활성탄을 제조하였다. 이 활성탄을 전기이중층에 적용한 결과, meso-pore구조의 미세구형활성탄은 전하전달저항의 저감 및 충방전율 수용능력 향상에 효과적인 영향을 나타내어 전기이중층 캐패시터의 성능향상을 위한 효과적인 전극물질이 될 수 있음을 확인할 수 있었다.

• 한국재료학회지
• /
• 제29권12호
• /
• pp.757-763
• /
• 2019

A stacked high-voltage (900 V) Al electrolytic capacitor made with ZrO₂ coated anode foils, which has not been studied so far, is realized and the effects of Zr-Al-O composite layer on the electric properties are discussed. Etched Al foils coated with ZrO₂ sol are anodized in 2-methyl-1,3-propanediol (MPD)-boric acid electrolyte. The anodized Al foils are assembled with stacked structure to prepare the capacitor. The capacitance and dissipation factor of the capacitor with ZrO₂ coated anode foils increase by 41 % and decrease by 50 %, respectively, in comparison with those of Al anode foils. Zr-Al-O composite dielectric layer is formed between separate crystalline ZrO₂ with high dielectric constant and amorphous Al₂O₃ with high ionic resistivity. This work suggests that the formation of a composite layer by coating valve metal oxide on etched Al foil surface and anodizing it in MPD-boric acid electrolyte is a promising approach for high voltage and volume efficiency of capacitors.

• 한국정보전자통신기술학회논문지
• /
• 제16권6호
• /
• pp.465-471
• /
• 2023

본 논문은 CMOS Image Sensor(CIS)에 사용되는 single-slope ADC(SS-ADC)의 노이즈와 출력의 지연을 개선한 비교기 구조를 제안한다. 노이즈와 출력의 지연 특성을 개선하기 위해 비교기의 첫 번째 단의 출력 노드와 두 번째 단의 출력 노드 사이에 커패시터를 삽입하여 miller effect를 이용한 비교기 구조를 설계하였다. 제안하는 비교기 구조는 작은 capacitor를 이용하여 노이즈와 출력의 지연 및 layout 면적을 개선하였다. Single slop ADC에서 사용되는 CDS 카운터는 T-filp flop과 bitwise inversion 회로를 사용하여 설계하였고 전력 소모와 속도가 개선되었다. 또한 single slop ADC는 analog correlated double sampling(CDS)와 digital CDS를 함께 동작하는 dual CDS를 수행한다. Dual CDS를 수행함으로써 fixed pattern noise(FPN), reset noise, ADC error를 줄여 이미지 품질이 향상된다. 제안하는 comparator 구조가 사용된 single-slope ADC는 0.18㎛ CMOS 공정으로 설계되었다.

• 한국재료학회지
• /
• 제32권7호
• /
• pp.313-319
• /
• 2022

Double-layer capacitors (DLCs) are developed with high surface electrodes to achieve a high capacitance value. In the present work, the initial bulk concentration of 1 mol/m³ and 3 mol /m³ are selected to show the consequential effects on the performance of a double-layer capacitor. A 1D model of COMSOL Multiphysics has been developed to analyze the electric field and potential in cell voltage, the electric displacement field and polarization induced by the field, and energy density in a double-layer structure. The electrostatics and the electric circuit modes in COMSOL are used to simulate the electrochemical processes in the double-layer structure. The analytical analysis of a double-layer capacitor with different initial bulk concentrations is investigated by using Poisson-Nernst-Plank equations. From the simulation results, the differential capacitance changes as a function of compact layer thickness and initial bulk concentration. The energy density varies with the differential capacitance and voltage window. The values of energy density are dominated by the interaction of ions in the solution and electrode surface.

• Journal of Power Electronics
• /
• 제15권3호
• /
• pp.587-601
• /
• 2015

A high step-up dc-dc converter is proposed for photovoltaic power systems in this paper. The proposed converter consists of an input current doubler, a symmetrical switched-capacitor doubler and an active-clamp circuit. The input current doubler minimizes the input current ripple. The symmetrical switched-capacitor doubler is composed of two symmetrical quasi-resonant switched-capacitor circuits, which share the leakage inductance of the transformer as a resonant inductor. The rectifier diodes (switched-capacitor circuit) are turned off at the zero current switching (ZCS) condition, so that the reverse-recovery problem of the diodes is removed. In addition, the symmetrical structure results in an output voltage ripple reduction because the voltage ripples of the charge/pump capacitors cancel each other out. Meanwhile, the voltage stress of the rectifier diodes is clamped at half of the output voltage. In addition, the active-clamp circuit clamps the voltage surges of the switches and recycles the energy of the transformer leakage inductance. Furthermore, pulse-width modulation plus phase angle shift (PPAS) is employed to control the output voltage. The operation principle of the converter is analyzed and experimental results obtained from a 400W prototype are presented to validate the performance of the proposed converter.

• Journal of Power Electronics
• /
• 제17권5호
• /
• pp.1173-1185
• /
• 2017

In this paper, a new single phase multilevel inverter topology with a single DC source is presented. The proposed topology is developed based on the concepts of the L-Z source inverter and the switched capacitor multilevel inverter. The input voltage to the proposed inverter is boosted by two steps: the first step by an impedance network and the second step by switched capacitor units. Compared to other existing topologies, the presented topology can produce a higher boosted multilevel output voltage while using a smaller number of components. In addition, it provides more flexibility to control boosting factor, size, cost and complexity of the inverter. The proposed inverter possesses all the advantages of the L-Z source inverter and the switched capacitor multilevel inverter like controlling the start-up inrush current and capacitor voltage balancing using a simple switching strategy. The operating principle and general expression for the different parameters of the proposed topology are presented in detail. A phase disposition pulse width modulation strategy has been developed to switch the inverter. The effectiveness of the topology is verified by extensive simulation and experimental studies on a 7-level inverter structure.