• Title/Summary/Keyword: Capacitor Structure

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A study on PZT capacitor on the glass substrate (유리 기판 위에서의 PZT 캐패시터에 관한 연구)

  • Ju, Pil-Yeon;Park, Young;Jeong, Kyu-Won;Song, Joon-Tae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.04b
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    • pp.80-83
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    • 2000
  • The post-annealing treatments on rf magnetron sputtered PZT($Pb_{1.05}(Zr_{0.52},\;Ti_{0.48})O_3$) thin films($4000{\AA}$) have been investigated for a structure of PZT/Pt/Ti/Coming glass(1737). Crystallization properties of PZT films were strongly dependent on RTA(Rapid Thermal Annealing) annealing temperature and time. We were able to obtain a perovskite structure of PZT at $650^{\circ}C$ and 10min. P-E curves of Pd/PZT/Pt capacitor demonstrate typical hysteresis loops. The measured values of $P_r$, $E_c$ were $8.1[{\mu}C/cm^2]$, 95[kV/cm] respectively. Polarization value decrease about 25% after $10^9$ cycles.

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A Study on Characteristics of Frequency Tunable Resonator using the Donut Type Defected Ground Structure (도넛형 결함접지면 구조를 이용한 주파수 가변 공진기 특성 연구)

  • Kim, Girae
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.2 no.4
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    • pp.59-64
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    • 2009
  • In this paper, we represent characteristics and equivalent circuit of donut type resonator of defected ground structure (DGS), and can control resonant frequency with chip capacitor. In General, DGS operates like with parallel LC resonator. We found out variation of resonance frequency when capacitor is placed on slot of DGS. If the chip capacitor replace with varactor diode, the resonance frequencies can be controlled by voltage. This tualable resonator can apply to voltage controlled oscillator and tunable bandpass filter.

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Ultra-small Marker Beacon Antenna with a Wide Frequency Tuneable Capacitive Plate

  • Park, Ju-Derk;Choi, Byeong-Cheol;Kim, Nam;Jung, Young-Bae
    • ETRI Journal
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    • v.38 no.5
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    • pp.879-884
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    • 2016
  • In this paper, an ultra-small marker beacon antenna operated in the VHF-band is proposed. This antenna has a modified linear IFA structure with a lumped capacitor and a capacitive plate for frequency tuning and impedance matching. The capacitive plate is directly connected to the end of a linear radiator and is separated from the antenna ground by 1 mm. The main operating frequency is mainly controlled by the size and dielectric constant of the capacitive plate. The lumped capacitor is useful for fine frequency tuning. Using the proposed structure, an ultra-small marker beacon antenna can be realized with a length of 0.04 ${\lambda}_0$.

Electrical charateristics of MIS BST thin films

  • Park, C.-S.;Mah, J.-P.
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.14 no.3
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    • pp.90-94
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    • 2004
  • The variation of electrical properties of (Ba,Sr)$TiO_3$ [BST] thin films for Metal-Insulator-Semiconductor (MIS) capacitors was investigated. BST thin films were deposited on p-Si(100) substrates by the RF magnetron sputtering with temperature range of 500~$600^{\circ}C$. The dielectric properties of MIS capacitors consisting of AUBST/$SiO_2$/Si sandwich structure were measured for various conditions. We examined the characteristics of MIS capacitor with various oxygen pressure, substrate temperature and (Ba+Sr)/Ti ratio. It was found that the leakage current was reduced in MIS capacitor with high quality $SiO_2$ layer was grown on bare p-Si substrate by thermal oxidation. The BST MIS structure showed relatively high capacitance even though it is the combination of high-dielectric BST thin films and $SiO_2$ layer. The charge state densities of the MIS capacitors and Current-voltage characteristics of the MIS capacitor were investigated. By applying $SiO_2$ layer between BST thin films and Si substrate, low leakage current of $10^{-10}$ order was observed.

Preparation of Micro-spherical Activated Carbon with Meso-porous Structure for the Electrode Materials of Electric Double Layer Capacitor (전기이중층 캐패시터 전극용 meso-pore구조의 미소구형 활성탄소 제조)

  • Um, Eui-Heum;Lee, Chul-Tae
    • Applied Chemistry for Engineering
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    • v.20 no.4
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    • pp.396-401
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    • 2009
  • A micro-spherical activated carbon with meso-pore structure of 52~64% and particle diameter of $2{\sim}10{\mu}m$ was prepared for the improvement electrochemical performance of activated carbon as electrode material for electric double layer capacitor. Resorcinol-formaldehyde resin was used as a carbon source in this preparation. According to electrochemical analysis of EDLC using this activated a carbon with showing effects to reduce charge transfer resistance and to increase rate capability, it was found out that micro-spherical activated carbon could be a good method as well as a material for enhancing the performance of electric double layer capacitor.

Stacked High Voltage Al Electrolytic Capacitors Using Zr-Al-O Composite Oxide

  • Zhang, Kaiqiang;Park, Sang-Shik
    • Korean Journal of Materials Research
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    • v.29 no.12
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    • pp.757-763
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    • 2019
  • A stacked high-voltage (900 V) Al electrolytic capacitor made with ZrO2 coated anode foils, which has not been studied so far, is realized and the effects of Zr-Al-O composite layer on the electric properties are discussed. Etched Al foils coated with ZrO2 sol are anodized in 2-methyl-1,3-propanediol (MPD)-boric acid electrolyte. The anodized Al foils are assembled with stacked structure to prepare the capacitor. The capacitance and dissipation factor of the capacitor with ZrO2 coated anode foils increase by 41 % and decrease by 50 %, respectively, in comparison with those of Al anode foils. Zr-Al-O composite dielectric layer is formed between separate crystalline ZrO2 with high dielectric constant and amorphous Al2O3 with high ionic resistivity. This work suggests that the formation of a composite layer by coating valve metal oxide on etched Al foil surface and anodizing it in MPD-boric acid electrolyte is a promising approach for high voltage and volume efficiency of capacitors.

Design of a Comparator with Improved Noise and Delay for a CMOS Single-Slope ADC with Dual CDS Scheme (Dual CDS를 수행하는 CMOS 단일 슬로프 ADC를 위한 개선된 잡음 및 지연시간을 가지는 비교기 설계)

  • Heon-Bin Jang;Jimin Cheon
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.16 no.6
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    • pp.465-471
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    • 2023
  • This paper proposes a comparator structure that improves the noise and output delay of a single-slope ADC(SS-ADC) used in CMOS Image Sensor (CIS). To improve the noise and delay characteristics of the output, a comparator structure using the miller effect is designed by inserting a capacitor between the output node of the first stage and the output node of the second stage of the comparator. The proposed comparator structure improves the noise, delay of the output, and layout area by using a small capacitor. The CDS counter used in the single slop ADC is designed using a T-filp flop and bitwise inversion circuit, which improves power consumption and speed. The single-slope ADC also performs dual CDS, which combines analog correlated double sampling (CDS) and digital CDS. By performing dual CDS, image quality is improved by reducing fixed pattern noise (FPN), reset noise, and ADC error. The single-slope ADC with the proposed comparator structure is designed in a 0.18-㎛ CMOS process.

Analysis of Bulk Concentration on Double-Layer Structure for Electrochemical Capacitors

  • Khaing, Khaing Nee Nee;Hla, Tin Tin
    • Korean Journal of Materials Research
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    • v.32 no.7
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    • pp.313-319
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    • 2022
  • Double-layer capacitors (DLCs) are developed with high surface electrodes to achieve a high capacitance value. In the present work, the initial bulk concentration of 1 mol/m3 and 3 mol /m3 are selected to show the consequential effects on the performance of a double-layer capacitor. A 1D model of COMSOL Multiphysics has been developed to analyze the electric field and potential in cell voltage, the electric displacement field and polarization induced by the field, and energy density in a double-layer structure. The electrostatics and the electric circuit modes in COMSOL are used to simulate the electrochemical processes in the double-layer structure. The analytical analysis of a double-layer capacitor with different initial bulk concentrations is investigated by using Poisson-Nernst-Plank equations. From the simulation results, the differential capacitance changes as a function of compact layer thickness and initial bulk concentration. The energy density varies with the differential capacitance and voltage window. The values of energy density are dominated by the interaction of ions in the solution and electrode surface.

High Step-up Active-Clamp Converter with an Input Current Doubler and a Symmetrical Switched-Capacitor Circuit

  • He, Liangzong;Zeng, Tao;Li, Tong;Liao, Yuxian;Zhou, Wei
    • Journal of Power Electronics
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    • v.15 no.3
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    • pp.587-601
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    • 2015
  • A high step-up dc-dc converter is proposed for photovoltaic power systems in this paper. The proposed converter consists of an input current doubler, a symmetrical switched-capacitor doubler and an active-clamp circuit. The input current doubler minimizes the input current ripple. The symmetrical switched-capacitor doubler is composed of two symmetrical quasi-resonant switched-capacitor circuits, which share the leakage inductance of the transformer as a resonant inductor. The rectifier diodes (switched-capacitor circuit) are turned off at the zero current switching (ZCS) condition, so that the reverse-recovery problem of the diodes is removed. In addition, the symmetrical structure results in an output voltage ripple reduction because the voltage ripples of the charge/pump capacitors cancel each other out. Meanwhile, the voltage stress of the rectifier diodes is clamped at half of the output voltage. In addition, the active-clamp circuit clamps the voltage surges of the switches and recycles the energy of the transformer leakage inductance. Furthermore, pulse-width modulation plus phase angle shift (PPAS) is employed to control the output voltage. The operation principle of the converter is analyzed and experimental results obtained from a 400W prototype are presented to validate the performance of the proposed converter.

A New Single Phase Multilevel Inverter Topology with Two-step Voltage Boosting Capability

  • Roy, Tapas;Sadhu, Pradip Kumar;Dasgupta, Abhijit
    • Journal of Power Electronics
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    • v.17 no.5
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    • pp.1173-1185
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    • 2017
  • In this paper, a new single phase multilevel inverter topology with a single DC source is presented. The proposed topology is developed based on the concepts of the L-Z source inverter and the switched capacitor multilevel inverter. The input voltage to the proposed inverter is boosted by two steps: the first step by an impedance network and the second step by switched capacitor units. Compared to other existing topologies, the presented topology can produce a higher boosted multilevel output voltage while using a smaller number of components. In addition, it provides more flexibility to control boosting factor, size, cost and complexity of the inverter. The proposed inverter possesses all the advantages of the L-Z source inverter and the switched capacitor multilevel inverter like controlling the start-up inrush current and capacitor voltage balancing using a simple switching strategy. The operating principle and general expression for the different parameters of the proposed topology are presented in detail. A phase disposition pulse width modulation strategy has been developed to switch the inverter. The effectiveness of the topology is verified by extensive simulation and experimental studies on a 7-level inverter structure.