• Journal of Power Electronics
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• v.18 no.2
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• pp.627-639
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• 2018

The fact that the reliability of IGBTs has become a more and more significant aspect of power converters has resulted in an increase in the research on the open circuit (OC) fault location of IGBTs. When an OC fault occurs, a zero-current phenomena exists and frequently appears, which can be found in a lot of the existing literature. In fact, fault variables have a very high correlation with the zero-current interval. In some cases, zero-current interval actually decides the most significant fault feature. However, very few of the previous studies really explain or prove the zero-current phenomena of the fault current. In this paper, the zero-current phenomena is explained and verified through mathematical derivation, based on two-level and three-level NPC static var generators (SVGs). Mathematical models of single OC fault are deduced and it is concluded that a zero-current interval with a certain length follows the OC faults for both two-level and NPC three-level SVGs. Both inductive and capacitive reactive power situations are considered. The unbalanced load situation is discussed. In addition, simulation and experimental results are presented to verify the correctness of the theoretical analysis.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.726-729
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• 2013

In this paper, low power and high slew rate CMOS rail to rail input/output opamp applicable for ouput buffer amp, in LCD source driver IC, is proposed. Proposed op-amp, is realized the characteristics of low power consumption and high slew rate adding the newly designed control stage of class-B to the conventional output stage of class-AB. From the simulation results, we know that the proposed opamp buffer can drive a 1000pF capacitive load with a 6.5V/us slew-rate, while drawing only the the power consumption of 1.19mW from 3.3V power supply.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.8
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• pp.13-18
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• 2005

The variation of discharge characteristics of an ac PDP was observed with the charge of scan electrode driving circuit. Conventional scan electrode driving circuit provides two switches per one scan line, and the suggested one can be constituted by one switch per one scan line with the consideration of capacitive load characteristic of an ac PDP. To verify the workability of the suggested scheme, the performances of the ac PDP was investigated. The dynamic voltage margin was slightly decreased with the adoption of the suggested scheme, which is estimated to result from the misfiring of unselected discharge cells due to the deformation of voltage level of the neighboring scan electrode. In the observation of the delay characteristics of addressing discharge, the performances of the conventional circuit and the suggested one are assumed to be equivalent.

• Journal of IKEEE
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• v.14 no.2
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• pp.51-57
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• 2010

A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.