• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1250-1259
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• 2012

In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-${\mu}m$ 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 ${\mu}W$ and 0.126 mm2, respectively.

• Journal of Power Electronics
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• v.15 no.1
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• pp.256-267
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• 2015

Grid-connected transformerless photovoltaic (PV) inverters (TPVIs) are increasingly dominating the market due to their higher efficiency, lower cost, lighter weight, and reduced size when compared to their transformer based counterparts. However, due to the lack of galvanic isolation in the low voltage grid interconnections of these inverters, the PV systems become vulnerable to leakage currents flowing through the grounded star point of the distribution transformer, the earth, and the distributed parasitic capacitance of the PV modules. These leakage currents are prohibitive, since they constitute an issue for safety, reliability, protection coordination, electromagnetic compatibility, and module lifetime. This paper investigates a wide range of multi-kW range power rating TPVI topologies and classifies them in terms of their leakage current attributes. This systematic classification places most topologies under a small number of classes with basic leakage current attributes. Thus, understanding and evaluating these topologies becomes an easy task. In addition, based on these observations, new topologies with reduced leakage current characteristics are proposed in this paper. Furthermore, the important efficiency and cost determining characteristics of converters are studied to allow design engineers to include cost and efficiency as deciding factors in selecting a converter topology for PV applications.

• Journal of Sensor Science and Technology
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• v.2 no.1
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• pp.19-27
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• 1993

Capacitive pressure sensor for low pressure measurements has been fabricated by using $n^{+}$ epitaxial layer electrochemical etching stop and glass-to-silicon electrostatic bonding technique. The sensor had hybrid configuration of a sensor chip, which consists of sensor capacitor and reference capacitor, and two output signal detection IC chips. A fabricated sensor, with a $1.0{\times}1.0 mm^{2}$ square size and a $10{\mu}m$ thick flat diaphragm, showed a 7.1 pF zero pressure capacitance, and 5.2 % F.S, sensitivity in 10 KPa pressure range. By using a capacitance to voltage converter, the thermal zero shift of 0.051 %F.S./$^{\circ}C$ and the thermal sensitivity shift of 0.12 %F.S./$^{\circ}C$ for temperature range of $5{\sim}45^{\circ}C$ were obtained.

• Journal of Sensor Science and Technology
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• v.13 no.2
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• pp.101-109
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• 2004

This paper presents a novel z-axis accelerometer with perfectly aligned vertical combs fabricated using the extended sacrificial bulk micromachining (extended SBM) process. The z-axis accelerometer is fabricated using only one (111) SOI wafer and two photo masks without wafer bonding or CMP processes as used by other research efforts that involve vertical combs. In our process, there is no misalignment in lateral gap between the upper and lower comb electrodes, because all critical dimensions including lateral gaps are defined using only one mask. The fabricated accelerometer has the structure thickness of $30{\mu}m$, the vertical offset of $12{\mu}m$, and lateral gap between electrodes of $4{\mu}m$. Torsional springs and asymmetric proof mass produce a vertical displacement when an external z-axis acceleration is applied, and capacitance change due to the vertical displacement of the comb is detected by charge-to-voltage converter. The signal-to-noise ratio of the modulated and demodulated output signal is 80 dB and 76.5 dB, respectively. The noise equivalent input acceleration resolution of the modulated and demodulated output signal is calculated to be $500{\mu}g$ and $748{\mu}g$. The scale factor and linearity of the accelerometer are measured to be 1.1 mV/g and 1.18% FSO, respectively.

• Journal of IKEEE
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• v.19 no.4
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• pp.506-513
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• 2015

In this paper, an output-capacitorless, low-dropout (LDO) regulator is designed, which consumes $4.5{\mu}A$ quiescent current. Proposed LDO regulator is realized using two amplifier for good load regulation and fast response time, which provide high gain, high bandwidth, and high slew rate. In addition, a one-shot current boosting circuit is added for current control to charge and discharge the parasitic capacitance at the pass transistor gate. As a result, response time is improved during load-current transition. The designed circuit is implemented through a $0.11-{\mu}m$ CMOS process. We experimentally verify output voltage fluctuation of 260mV and recovery time of $0.8{\mu}s$ at maximum load current 200mA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.