• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1125-1128
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• 2003

This paper presents the design method of a Colpitts type oscillator with coplanar waveguide(CPW) structures in the range of Ka-band frequency for transmitter and receiver modules. Series short stubs of CPW patterns provide inductances and capacitances in the range of Ka-band which can be expressed as a CLC-$\pi$ equivalent circuit. The experimentation has employed ro4003 substrates as a CPW substrate which has a dielectric constant of 3.38 and a signal and ground space of 100um. A method of momentum simulation for the CPW patterns has performed with an ADS software tool of Hewlett-Packard Corp. Inductance and capacitance circuits of a Colpitts oscillator was interconnected to a MESFET with CPW bend structures of including the input and output impedance matching circuits of the active transistor. Circuit parameters for impedance matching were determined through the network conversion to the equivalent length of CPW transmission lines by using T-network 1 $\pi$-network conversion circuit. A Colpitts oscillator was fabricated on the substrate of a area of 8.5mm x 17.4mm with a MESFET of Fujitsu FMM5704X and CPW series short stubs. The design suggested the possibility of realizing oscillators on a planar surface for the wireless system of tansmitter and receiver modules in the frequency range of 30GHz

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.36-46
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• 2010

In multi-GHz RF ICs and high-speed digital interfaces, ESD protection devices introduce considerable parasitic capacitance and resistance to inputs and outputs, thereby degrading the RF performance, such as input/output matching, gain, and noise figure. In this paper, the impact of ESD protection devices on the performance of RF ICs is investigated and design methodologies to minimize this impact are discussed. With RF and ESD test results, the 'RF/ESD co-design' method is discussed and compared to the conventional RF ESD protection method which focuses on minimizing the device size.

• Journal of Power Electronics
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• v.16 no.3
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• pp.832-839
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• 2016

In this study, the performance of a direct current (DC)-DC buck converter is analyzed in the presence of non-idealities in passive components and semiconductor devices. The effect of these non-idealities on the various design issues of a DC-DC buck converter is studied. An improved expression for duty cycle is developed to compensate the losses that occur because of the non-idealities. The design equations for inductor and capacitor calculation are modified based on this improved expression. The effect of the variation in capacitor equivalent series resistance (ESR) on output voltage ripple (OVR) is analyzed in detail. It is observed that the value of required capacitance increases with ESR. However, beyond a maximum value of ESR (r_c,max), the capacitor is unable to maintain OVR within a specified limit. The expression of r_c,max is derived in terms of specified OVR and inductor current ripple. Finally, these theoretical studies are validated through MATLAB simulation and experimental results.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.470-476
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• 2000

This paper describes an IP design of a low-power microcontroller using an architecture level design methodology instead of a transistor level. To reduce switching capacitance, the register-toregister data transfer is adopted to frequently used register transfer micro-operations. Also, distributed buffers are proposed to reduce a input data rising edge time. To reduce power consumption without any loss of performance, pipeline processing should be used. In this paper, a 4-stage pipelined datapath being able to process CISC instructions is designed. Designed microcontroller lessens power consumption by 20%. To measure a power consumption, the SYNOPSYS EPIC powermill is used.

• Journal of the Korean Society of Clothing and Textiles
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• v.45 no.1
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• pp.168-179
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• 2021

This study presents and develops a textile type touch sensor structural design that is easy to implement. First, the design of the touch sensor circuit finds the size of the switch with the easiest finger contact and selects a structure with a long circuit with the lowest resistance value. An experiment is performed on a change in an electrostatic capacitance value that accompanies the distance on the electrode and the magnitude of the electrode area of the structure; however, the structure having the distance on the electrode and the large electrode area shows the best resistance change. The laundry assessment was conducted three times at a time and ten times at a time with an average standard deviation less than one ohm, with little change in resistance. Consequently, there were no problems with durability and performance for laundry. Finally, in the bending evaluation, the difference in resistance can be seen between 1-2 ohms and was developed as a smart wearable in the future; in addition, there was no problem as a difference in resistance can be seen between 1 and 2 ohms.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.131-131
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.4126-4130
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• 2012

In this paper, we proposed planar spiral inductors based on AC coupling for high-frequency wireless signal transmission. Design and characteristics of various structures of the inductor were analyzed. Capacitance between the inductors can be reduced by positioning two thin-film inductors in parallel. So two structures were proposed. First structure is inter-diagonal structure. This structure was made not to overlap the wire part of the paralleled two inductors. Second structure is On-chip type structure that the two thin-film inductors were in parallel but located on diagonal line not to face each other. The resonance in this structure was reduced from twice to once by increasing horizontal distance between the two thin-film inductors, because the capacitance effect between the two thin-film inductors decreases when the distance between the two inductors increases.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1587_1588
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• 2009

In this paper, PCB embedded balanced-to-unbalamced duplexer using coupled LC resonator was introduced for low cost dualband WiMax front-end-module application. In order to obtain the function of bandpass filter and balun transformer, proposed duplexer was configured by using magnetically coupled LC resonator. Out-of-band suppression was enhanced by applying two m-Derived transform circuits to obtain transmission zeros at 2GHz and 4.8GHz. In order to reduce the size of embedded duplexer, BaSrTiO3 (BST) composite high Dk RCC film was applied to improve the capacitance density. This high Dk film provided the capacitance density of 12.2 pF/mm2. The simulation results shows that fabricated duplexer had an insertion loss of 2.9dB and 5.5dB and return loss of 15dB and 16dB for 2.5GHz~2.6GHz and 3.5GHz~3.6GHz, respectively. The maximum magnitude and phase imbalance were 0.01dB and 0.17dB, and 1degree and 2degree in its passband, respectively. The out-of-band suppression was observed approximately 29dB and 40dB below 1.9GHz and over 4.5GHz, respectively. It has a volume of 6 mm $\times$ 7 mm $\times$ 0.7 mm (height).

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.5
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• pp.455-461
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• 2017

In this paper, a local DL (Data Line) sensing method with smaller parasitic capacitance replacing the previous distributed DB sensing method with large parasitic capacitance is proposed to reduce the time to transfer BL (Bit Line) voltage to DL in the read mode. A new BL switching circuit turning on NMOS switches faster is also proposed. Furthermore, the access time is reduced to 35.63ns from 40ns in the read mode and thus meets the requirement since BL node voltage is clamped at 0.6V by a DL clamping circuit instead of precharging the node to VDD-VT and a differential amplifier are used. The layout size of the designed 512Kb EEPROM memory IP based on a $0.13{\mu}m$ BCD is $923.4{\mu}m{\times}1150.96{\mu}m$ ($=1.063mm^2$).