• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.1776-1778
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• 2000

The demands placed on portable wireless communication equipment include low cost, low supply voltage, low power, dissipation, low noise, high frequency of operation, and low distortion. These design requirements cannot be met satisfactorily in many cases without the use of RF inductors. However, implementing the inductor on-chip has been regarded as an impractical task because of excessive substrate capacitance and substantial resistive losses due to metallization and the conductive silicon substrate. Hence, there is a great incentive to design, optimize, and model spiral inductors on Si substrate. So, we analyzed a chip inductors using electromagnetic analysis and established a set of design rules for rectangular spiral inductors.

• 전력전자학회논문지
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• 제22권6호
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• pp.504-509
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• 2017

This paper proposes a procedure for designing a resonant network for induction cookers that enables the induction heating of magnetic and non-magnetic vessels. In order to design such network, the range of operating frequency must be determined according to the material of the vessels by measuring several parameters, such as equivalent resistance and inductance, which are reflected in the working coil of the vessels. Through this process, the capacitance of the resonant capacitor is determined. The PSIM simulation and experiment results verify the feasibility of the proposed design and the heating performance of the designed resonant network.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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• pp.155-158
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• 2004

This paper presents a CPW patch antenna with $\lambda/2$ CPW transmission lines. Through the full-wave simulation and the equations of gap capacitance, the dimensions of the CPW transmission lines and resonance circuit components are extracted. Using extracted dimensions, we designed and implemented CPW patch antennas in the range of frequency of 5GHz.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.400-403
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• 2000

This paper deals with the active clamp ZVS flyback converter for semiconductor plasma etching system. The proposed converter has the characteristics of the good power facter low switching noise and efficiency improvement. The characteristics are verified through simulation results. Furthermore the ringing effect due to output capacitance of the main switch can be eliminated by use of active clamp circuit.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2014년도 춘계학술대회 논문집
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• pp.392-393
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• 2014

Multilayer ceramic capacitors (MLCCs) have become one kind of the most widely used electrical components in recent decades. And the technology of MLCCs is developing continuously towards a direction of high capacitance and miniaturization. While the tiny thickness and the large quantity of the layers often make it very troublesome to do analysis with the full model MLCCs. In order to solve this problem, reduced model with fewer layers of MLCC was designed and verified in this paper.

• Journal of Information Display
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• 제6권1호
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• pp.17-21
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• 2005

We explored a new way of designing dynamic logic gates with low temperature polysilicon thin film transistors to increase the speed. The proposed architecture of logic gates utilizes the structural advantage of smaller junction capacitance of thin film transistors. This method effectively blocks leakage of current through the thin film transistors. Furthermore, the number of transistors used in logic gates is reduced thereby reducing power consumption and chip area. Through HSPICE .simulation, it is confirmed that the circuit speed is also improved in all logic gates designed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.523-524
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• 2008

Proposed battery charger is a economic candidate because that is simple and small size. The circuit has linearly operational power stage. That use small size buffer with small driving current and large power MOS gate capacitance. The simulation result show that charging current is stable and has low ripple.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1058-1061
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• 2002

This paper presents the method of low power optimization considering the glitch reduction in CMOS circuits. Our algorithm utilizes the information of MOS size, the load capacitance of fan-out, and input slew to calculate the output waveform by using the linear signal model. Therefore, the accurate waveform of glitch can be obtained for estimation of power dissipation caused by glitches. Our algorithm is applied to ISCAS’85 benchmark circuits and experimental results show 23% glitch reduction and 11% total power reduction.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.13-14
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• 2000

21.6" a-Si:H TFT array for direct conversion X-ray detector with 2480 by 3072 pixel is successfully developed. To obtain good X-ray image quality, novel structure, storage on BCB structure, is proposed. The structure reduces the parasitic capacitance of data line, one of the main sources of signal noise. Also, the structure shows higher failure resistance against defects than that of the old design.

• 한국산업정보학회:학술대회논문집
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• 한국산업정보학회 2002년도 춘계학술대회 논문집
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• pp.195-199
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• 2002

This paper describes the effect of substrate back bias of CMOS Inverter. When the substrate back bias applied in body, the MOS transistor threshold voltage increased and drain saturation current decreased. The back gate reverse bias or substrate bias has been widely utilized and the following advantage has suppressing subthreshold leakage, lowering parasitic junction capacitance, preventing latch up or parasitic bipolar transistor, etc. When the reverse voltage applied substrate, this paper stimulated the propagation delay time CMOS inverter.