• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.968-969
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• 2015

This paper proposes a novel analysis method for calculating inverter DC bus capacitance and line reactor parameters. In the realization process, DC bus capacitance parameter, and ripple current, life of DC bus capacitor, interaction between DC bus capacitance can be calculated by using Newton-Raphson procedure. The design scheme of DC bus capacitor and line reactor, specific parameters such as capacitance, loss, ripple current, central average temperature, life, ripple current, loss, size, central temperature of the reactor were given. Simulation results show that this scheme can accurately calculate the DC bus capacitance and line reactor parameters. Compared with calculation result of references, cost and volume are half. The indicators meet the demand of practical engineering. It had affirmed precision of the analytical method and verified correctness and feasibility of this method.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.25 no.4
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• pp.307-311
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• 2016

Several types of supercapacitors have been developed for energy storage systems. Among them, the hybrid type has advantages such as a large capacitance per weight compared with the electric double-layer capacitator type. In this study, constant current charging and discharging tests were conducted for recently developed hybrid-type supercapacitors. Based on the experimental results, the capacitance and equivalent series resistance were obtained. The capacitance was larger than the designed capacitance at a low current but became small at a high current. In addition, the capacitance depended on the cell voltage. These results can be used to design an energy storage system.

• Journal of information and communication convergence engineering
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• v.19 no.4
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• pp.263-268
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• 2021

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.

• Journal of Powder Materials
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• v.30 no.4
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• pp.310-317
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• 2023

Small-film-type ion sensors are garnering considerable interest in the fields of wearable healthcare and home-based monitoring systems. The performance of these sensors primarily relies on electrode capacitance, often employing nanocomposite materials composed of nano- and sub-micrometer particles. Traditional techniques for enhancing capacitance involve the creation of nanoparticles on film electrodes, which require cost-intensive and complex chemical synthesis processes, followed by additional coating optimization. In this study, we introduce a simple one-step electrochemical method for fabricating gold nanoparticles on a carbon nanotube (Au NP-CNT) electrode surface through cyclic voltammetry deposition. Furthermore, we assess the improvement in capacitance by distinguishing between the electrical double-layer capacitance and diffusion-controlled capacitance, thereby clarifying the principles underpinning the material design. The Au NP-CNT electrode maintains its stability and sensitivity for up to 50 d, signifying its potential for advanced ion sensing. Additionally, integration with a mobile wireless data system highlights the versatility of the sensor for health applications.

• Journal of electromagnetic engineering and science
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• v.17 no.4
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• pp.221-227
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• 2017

A new approach to designing a broadband and highly efficient class-E power amplifier based on nonlinear shunt capacitance analysis is proposed. The nonlinear shunt capacitance method accurately extracts optimum class-E power amplifier parameters, including an external shunt capacitance and an output impedance, at different frequencies. The dependence of the former parameter on the frequency is considered to select an optimal value of external shunt capacitor. Then, upon determining the latter parameter, an output matching network is optimized to obtain the highest efficiency across the bandwidth of interest. An analytical approach is presented to design the broadband class-E power amplifier of a MOSFET transistor. The proposed method is experimentally verified by a 140-170 MHz class-E power amplifier design with maximum added power efficiency of 82% and output power of 34 dBm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.61-72
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• 2005

This paper proposes a method which efficiently allocates decoupling capacitance to reduce power supply noise at the floorplan level. We observe problems of previous approach that the decoupling capacitance of each module was overestimated and the power supply noises of modules were changed by inserting additional area for decoupling capacitance, and then suggest a new approach. And, we also present a simple heuristic method which can effectively allocate white space modules for decoupling capacitance area within more faster time instead of LP technique. Experimental results show that our approach can reduce the area of decoupling capacitance to average 7.9 percent compared with Zhao's approach in [4]. Therefore both total area and wire length of nniflm result are decreased. Also, we confirm that our approach solves well the problem caused by inserting additional area. In execution time comparison, our approach shows average 11.6 percent improvement.

• Nuclear Engineering and Technology
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• v.52 no.7
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• pp.1503-1510
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• 2020

Ultra-low noise charge sensitive amplifiers (CSAs) based on various types of circuit board substrates, such as FR4, Teflon, and ceramics (Al₂O₃) with two different designs, PA1 and PA2, have been developed. They were tested to see the noise effect from the dielectric loss of the substrate capacitance before and after irradiation. If the electronic noise from the CSAs is to be minimized and the energy resolution enhanced, the shaping time has to be optimized for the detector, and a small feedback capacitance of the CSA is favorable for a better SNR. Teflon- and ceramic-based PA1 design CSAs showed better noise performance than the FR4-based one, but the Teflon-based PA1 design showed better sensitivity than ceramic based one at a low detector capacitance (<10 pF). In the PA2 design, the equivalent noise and the sensitivity were 0.52 keV FWHM for a silicon detector and 7.2 mV/fC, respectively, with 2 ㎲ peaking time and 0.1 pF detector capacitance. After 10, 100, 10³, 10⁴, and 10⁵ Gy irradiation the ENC and sensitivity characteristics of the developed CSAs based on three different substrate materials are also discussed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.4
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• pp.620-627
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• 1990

A software tool implementing cascaded SCF (Switched Capacitor Filter) is developed. A comprehensive procedure is described for the design of cascaded SCF, and some design considerations are discussed. In program several user-selectable filter approximation techniques, and two optimising methods which reduce the total capacitance are included. Analysis of the partial positive feedback and the effect of clock frequency to total capacitance are presented in detail. Two pratical examples are given to prove its validity in reducing the total capacitance. Developed tool can be used for general SCF generator.

• Structural Monitoring and Maintenance
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• v.3 no.3
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• pp.297-314
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• 2016

As the study of internal corrosion of pipeline need a large number of experiments as well as long time, so there is a need for new computational technique to expand the spectrum of the results and to save time. The present work represents a new non-destructive evaluation (NDE) technique for detecting the internal corrosion inside pipeline by evaluating the dielectric properties of steel pipe at room temperature by using electrical capacitance sensor (ECS), then predict the effect of pipeline environment temperature (${\theta}$) on the corrosion rates by designing an efficient artificial neural network (ANN) architecture. ECS consists of number of electrodes mounted on the outer surface of pipeline, the sensor shape, electrode configuration, and the number of electrodes that comprise three key elements of two dimensional capacitance sensors are illustrated. The variation in the dielectric signatures was employed to design electrical capacitance sensor (ECS) with high sensitivity to detect such defects. The rules of 24-electrode sensor parameters such as capacitance, capacitance change, and change rate of capacitance are discussed by ANSYS and MATLAB, which are combined to simulate sensor characteristic. A feed-forward neural network (FFNN) structure are applied, trained and tested to predict the finite element (FE) results of corrosion rates under room temperature, and then used the trained FFNN to predict corrosion rates at different temperature using MATLAB neural network toolbox. The FE results are in excellent agreement with an FFNN results, thus validating the accuracy and reliability of the proposed technique and leads to better understanding of the corrosion mechanism under different pipeline environmental temperature.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.638-648
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• 2003

An active capacitance circuit is analyzed in depth and its application to active RF BPF with low noise figure is discussed. The characteristics of the active capacitance circuit made of FET[1] exhibits negative resistance and conventional capacitance, which is easily controlled. However, it is difficult to make the negative resistance adequate in the designated frequency range due to the lack of detailed analysis, which could make an active circuit unstable as the frequency is going higher or lower. In this paper, we analyzed the negative resistance characteristics of active capacitance circuits and also presented the method that the flatness of passband can be controlled. Finally we have designed a 4-stage active BPE, which results in bandwidth of 100 MHz, 0,04 dB insertion loss, 0.2 dB ripple, and noise figure of 2.4 dB at 1.75 GHz band.