• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.579-580
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• 2008

DRAM설계시 DDR2에서부터 고속 동작으로 인해 반송파에 의한 신호외곡으로 impedance matching의 필요성이 대두되었다. 이로 인해 제안된 방법은 외부 Termination 저항(RZQ)을 기준으로 impedance matching을 위한 Rtt 저항의 생성이다.[1] 제안된 ZQ Calibration 회로는 기존의conventional ZQ Calibration 회로에 After ZQ calibration block을 추가하여 한 번 더 교정함으로써 마지막 PMOS Array와 NMOS Array 저항 값이 Termination 저항 값에 가깝도록 설계하였다. 따라 전력효율은 그대로 유지하면서 ${\Delta}VM$의 오차범위를 기존의 ${\pm}5%$이내에서 skew 조건에 따라 ${\pm}1.33%$까지 향상시키는 것을 볼 수 있다. (JEDEC spec. ${\pm}5%$이내).

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1109-1112
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• 2003

Information technology has enabled mass standards calibration to be performed through internet. For this, an automatic weight handler was manufactured. During the operation the images of weight operation and the system are provided via the measurement system and a web server. The measurement system consists of a balance, a weight handler, instruments for environment measurement and a PC. The weight handler automatically loads and unloads weights on and from the weighing pan. The weight handler allows 6 series weights to be operated for weight calibration of 100-50-20-20-10-10 gram series weight. This capability could be used for "remote training" for series weight calibration.

• Journal of Institute of Control, Robotics and Systems
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• v.2 no.3
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• pp.188-193
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• 1996

In this paper, an integrated navigation system based on GPS(Global Positioning System) and Dead-Reckoning (DR) is designed. For the calibration of DR, a self-calibration method and a GPS-based calibration method are proposed. From the field-test results, it is shown that DR can be successfully calibrated by the two proposed calibration methods. Also, a cascaded filter approach and a mixed-measurement algorithm are employed for GPS/DR integration. By using the newly proposed mixed-measurement algorithm, it is shown in simulation that the position error becomes smaller than by using only DR even if the number of visible GPS satellites is less than 4.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.469-471
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• 2022

This paper presents an implementation of a calibration circuit to correct the gain error, DC offset and sampling clock phase error generated in the process of converting digital pixels to analog pixels to drive an analog-driven 4K UHD LCOS panel. The proposed calibration circuit consists of a gain and DC offset adjustment circuit and a sampling clock phase adjustment circuit. The calibration circuit is implemented with an FPGA device, and video amplifiers.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.11
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• pp.1174-1179
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• 2008

Many modeling and calibration methods have been developed to analyze and design the biological wastewater treatment process. For the systematic use of activated sludge model (ASM) in a real treatment process, a most important step in this usage is a calibration which can find a key parameter set of ASM, which depends on the microorganism communities and the process conditions of the plants. In this paper, a standardized calibration protocol of the ASM model is developed. First, a weighted effluent quality index(WEQI) is suggested far a calibration protocol. Second, the most sensitive parameter set is determined by a sensitive analysis based on WEQI and then a parameter optimization method are used for a systematic calibration of key parameters. The proposed method is applied to a calibration problems of the single carbon removal process. The results of the sensitivity analysis and parameter estimation based on a WEQI shows a quite reasonable parameter set and precisely estimated parameters, which can improve the quality and the efficiency of the modeling and the prediction of ASM model. Moreover, it can be used for a calibration scheme of other biological processes, such as sequence batch reactor, anaerobic digestion process with a dedicated methodology.

• The Journal of Korea Robotics Society
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• v.9 no.1
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• pp.39-47
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• 2014

Odometry using wheel encoders is one of the fundamental techniques for the pose estimation of wheeled mobile robots. However, odometry has a drawback that the position errors are accumulated when the travel distance increases. Therefore, position errors are required to be reduced using appropriate calibration schemes. The UMBmark method is the one of the widely used calibration schemes for two wheel differential drive robots. In UMBmark method, it is assumed that odometry error sources are independent. However, there is coupled effect of odometry error sources. In this paper, a new calibration scheme by considering the coupled effect of error sources is proposed. We also propose the test track design for the proposed calibration scheme. The numerical simulation and experimental results show that the odometry accuracy can be improved by the proposed calibration scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.420-423
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• 2015

This paper proposes a method of non-linearity error detection and calibration for binary-weighted charge-driven DACs. In general, the non-linearity errors of DACs often occur due to the mismatch of layout designs or process variation, even when careful layout design methods and process calibration are adopted. Since such errors can substantially degrade the SNDR performance of DAC, it is crucial to accurately measure the errors and calibrate the design mismatches. The proposed method employs 2 identical DAC circuits. The 2 DACs are sweeped, respectively, by using 2 digital input counters with a fixed difference. A comparator identifies any non-linearity errors larger than an acceptable discrepancy. We also propose a calibration method that can fine-tune the DAC's capacitor sizes iteratively until the comparator finds no further errors. Simulations are presented, which show that the proposed method is effective to detect the non-linearity errors and calibrate the capacitor mismatches of a 12-bit DAC design of binary-weighted charge-driven structure.

• The KSFM Journal of Fluid Machinery
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• v.5 no.1 s.14
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• pp.62-67
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• 2002

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.06a
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• pp.321-322
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• 2007

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.18-27
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• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.