• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2891-2902
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• 1997

This paper presents an analysis on the optimal partitioning configuration of cache (memory) for meeting deadlines of periodic and aperiodic real-time task set. Our goal is not only to decrease the deadline missing ratio of each task by minimizing the task utilization, but also to allocate another tasks to idle spaces of cache. For this reason, we suggest an algorithm so that tasks could be allocated to cache segments. Here, the set of cache segments allocated tasks is called a cache partitioning configuration. Based on how tasks allocate to cache segments, we can get various cache partitioning configurations. From these configurations, we obtain the boundary of task utilization that tasks are possible to schedule, and analyze the cache optimal partitioning configuration that can be executed to minimize the task utilization.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.435-444
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• 2007

Caching web pages is an important part of web infrastructures. The effects of caching service are even more pronounced for wireless infrastructures due to their limited bandwidth. Medium to large-scale infrastructures deploy a cluster of servers to solve the scalability problem and hot spot problem inherent in caching. In this paper we present scheduling scheme based on cache utilization in a wireless internet proxy server cluster environment. The proposed method uses cache utilization for distributing evenly client requests to a cluster of cache servers and solving hot spot problem. We have implemented our approach and performed various experiments using publicly available traces. Experimental results on a cluster of 16 cache servers demonstrate that the proposed hashing method gives 45% to 114% Performance improvement over other widely used methods while addressing the hot spot problem.

• Journal of KIISE:Databases
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• v.34 no.4
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• pp.328-342
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• 2007

We propose a new cache conscious indexing structure for processing frequently updated data efficiently. Our proposed index structure is based on a KDB-Tree, one of the representative index structures based on space partitioning techniques. In this paper, we propose a data compression technique and a pointer elimination technique to increase the utilization of a cache line. To show our proposed index structure's superiority, we compare our index structure with variants of the CR-tree(e.g. the FF CR-tree and the SE CR-tree) in a variety of environments. As a result, our experimental results show that the proposed index structure achieves about 85%, 97%, and 86% performance improvements over the existing index structures in terms of insertion, update and cache-utilization, respectively.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.238-241
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• 2002

With the popularity of utilization of the Internet among people, the amount of data in the network rapidly increased. So that, the fall of response time from WWW server, which is caused by the network traffic and the burden on m server, has become more of an issue. This problem is encouraged the rearch by redundancy of requesting the same pages by many people, even though they browse the same the ones. To reduce these redundancy, WWW cache server is used commonly in order to store m page data and reuse them. However, the technical uses of WWW cache that different from CPU and Disk cache, is known for its difficulty of improving the cache hit rate. Consecuently, it is difficult to choose effective WWW data to be stored from all data flowing through the WWW cache server. On the other hand, there are room for improvement in commonly used cache replacement algorithms by WWW cache server. In our study, we try to realize a WWW cache server that stresses on the improvement of the stresses of response time. To this end, we propose the new cache replacement algorithm by focusing on the utilizable information of network distance from the WWW cache server to WWW server that possessing the page data of the user requesting.

• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.6
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• pp.289-297
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• 2020

Although flash disks are being used widely instead of hard disks, it is difficult to optimize for effective utilization of flash disks because overwrite in place is impossible and the power consumption and time required for read, write, and erase operations are all different. One of these optimization issues is a cache management strategy to minimize write operations. The cache operates at two levels: an operating system equipped with flash disks and a translation layer within the flash disk. Most studies deal with the operating system-level cache strategy. In this study, we implement and analyse the DPW-LRU algorithm which is one of the recently proposed operating system cache replacement algorithms to apply to FTL, and grope with some improvements. As a result of the experiment, the DPW-LRU algorithm maintained superiority even in the FTL environment, and showed better performance with a slight improvement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1815-1827
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• 1993

In this paper, we evaluate the performance of a Futurebus based multiprocessor system with MESI cache coherence protocol for four bus transaction types. Graphical symbols and compiler of SLAM II are used in modeling and simulation. A steady-state probability of each state for MESI protocol is computed by a Markov chain. The probability of each state is used as an input value for a correct simulation. Processor utilization, memory utilization, bus utilization, and the waiting time for bus arbitration are measured in terms of the number of processors, the hit ratio of cache memory, the probability of internal operation, and bus bandwidth.

• Proceedings of the Korea Contents Association Conference
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• 2004.11a
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• pp.448-452
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• 2004

Cache sensitive $B^+-trees$ with partial keys is cache sensitive tree using both key compression and pointer compression. Although conventional cache sensitive trees consider individuallykey compression and pointer compression, cache sensitive $B^+-trees$ with partial keys make more cache utilization by compressing both key and pointer. We implement bulkload and search algorithms of cache sensitive $B^+-trees$ with partial key. And out performance studies show that cache sensitive $B^+-trees$ with partial key is better than $B^+-trees$ and Simple Prefix $B^+-trees$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.57-68
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• 1993

In this paper, we describe a multiprocessor system using the HiPi bus with pended protocol and multiple cache memories, and evalute the performance of the multiprocessor system in terms of processor utilization for various cache coherence protocols. The HiPi bus is delveloped as the shared bus of TICOM II which is a main computer system to establish a nation-wide computing network in ETRI. The HiPi bus has high data transfer rate, but it doesn't allow cache-to-cache transfer. In order to evaluate the effect of cache-to-cache transfer upon the performance of system and to choose a best-performed protocol for HiPi bus, we simulate as follows: First, we analyze the performance of multiprocessor system with HiPi bus in terms of processor utilizatIOn through simulation. Each of cache coherence protocol is described by state transition diagram, and then the probability of each state is calculated by Markov steady state. The calculated probability of each state is used as input parameters of simulation, and modeling and simulation are implemented and performed by using SLAM II graphic symbols and language. Second, we propose the HiPi bus which supports cache-to-cache transfer, and analyze the performance of multiprocessor system with proposed HiPi bus in terms of processor utilization through simulation. Considered cache coherence protocols for the simulation are Write-through, Write-once, Berkely, Synapse, Illinois, Firefly, and Dragon.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.129-134
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• 2015

This paper analyzes file access characteristics of smartphone apps and finds that a large portion of file writes are performed only once. Based on this observation, we present a new buffer cache management scheme that considers this characteristics. Buffer cache improves storage performance by maintaining hot file data in memory thereby servicing subsequent requests without storage accesses. However, it should flush modified data to storage in order to resist system crashes. The proposed scheme evicts cache data that has been written only once upon flushes, thus improving cache space utilization. Simulation experiments show that the proposed scheme improves cache hit ratio by 5-33% and power consumption by 27-92%.

• Journal of KIISE:Databases
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• v.34 no.3
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• pp.217-231
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• 2007

Frequent disconnection is connected directly to client's cache consistency problem in Mobile Computing environment. For solving cache consistency problem, research about Invalidation Report is studied. But, existent invalidation report structure comes with increase of size of invalidation report structure and decline of cache efficiency if quantity of data become much, or quantity of updated data increases. Also, while existent method confirms whole cache, invalidation report doesn't support selective listening. This paper proposes TTCI(Timestamp Tree-based Cache Invalidation scheme) as invalidation report structure that solve problem of these existing schemes and improve efficiency. We can make TTCI using timestamp of updated data, composing timestamp tree and list ID of data in updated order. If we utilize this, each client can confirm correct information in point that become own disconnecting and increase cache utilization ratio. Also, we can pare down client's resources consumption by selective listening using tree structure. We experimented in comparison with DRCI(Dual-Report Cache Invalidation) that is existent techniques to verify such efficiency of TTCI scheme.