• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 춘계학술대회
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• pp.1315-1320
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• 2003

The thermal expansion coefficient, which causes the micro failure at the interfacial state of thin films is necessary to consider for proper designing MEMS. The effect of temperature on the coefficient of thermal expansion(CTE) of $SiO_2$ and $Si_3N_4$ film was investigated. Thermal strain induced by mismatch of CTE between substrate and thin film continuously measured with resolution-improved electronic speckle pattern interferometry(ESPI). The thermal stress induced by mismatch of CTE derivate through thermal strain. The thermal expansion coefficients of thin film were calculated with the general equation of CTE and thermal stress in thin films, and it confirmed that CTE of $SiO_2$changed from $0.25{\times}10^{-6}/^{\circ}C$ to $1.4{\times}10^{-6}/^{\circ}C$ with temperature increasing from 50 to $600^{\circ}C$

• Journal of Welding and Joining
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• 제32권3호
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• pp.68-73
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• 2014

Among through silicon via (TSV) technologies, for replacing Cu filling method, the method of molten solder filling has been proposed to reduce filling cost and filling time. However, because Sn alloy which has a high coefficient of thermal expansion (CTE) than Cu, CTE mismatch between Si and molten solder induced higher thermal stress than Cu filling method. This thermal stress can deteriorate reliability of TSV by forming defects like void, crack and so on. Therefore, we fabricated SiC composite filling material which had a low CTE for reducing thermal stress in TSV. To add SiC nano particles to molten solder, ball-typed SiC clusters, which were formed with Sn powders and SiC nano particles by ball mill process, put into molten Sn and then, nano particle-dispersed SiC composite filling material was produced. In the case of 1 wt.% of SiC particle, the CTE showed a lowest value which was a $14.8ppm/^{\circ}C$ and this value was lower than CTE of Cu. Up to 1 wt.% of SiC particle, Young's modulus increased as wt.% of SiC particle increased. And also, we observed cross-sectioned TSV which was filled with 1 wt.% of SiC particle and we confirmed a possibility of SiC composite material as a TSV filling material.

• 한국생산제조학회지
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• 제22권1호
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• pp.168-172
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• 2013

In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.

• 대한기계학회논문집A
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• 제28권11호
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• pp.1646-1655
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• 2004

A description of the basic principles of moire interferometry leads to the design of a eight-mirror four-beam interferometer for obtaining fringe patterns representing contour-maps of in-Plane displacements. The technique is implemented by the optical system using an environmental chamber for submicro-displacement mesurement. In order to estimate the reliability and applicabili쇼 of the system developed, the measurement of coefficient of thermal expansion (CTE) for a aluminium block is performed. Consequently, the system is applied to the measurement of thermal deformation of a WB-PBGA package assembly. Temperature dependent analyses of global and local deformations are presented to study the effect of the mismatch of CTE between materials composed of the package assemblies. Bending displacements of the packages and average strains of solder balls are documented. Thermal induced displacements calculated by FEM agree quantitatively with experimental results.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 춘계학술대회 논문집
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• pp.873-874
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• 2012

• 마이크로전자및패키징학회지
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• 제13권4호
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• pp.1-7
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• 2006

WLCSP(wafer level chip size package)는 웨이퍼 레벨에서 패키지 공정이 이루어지는 차세대 패키지 중 하나이다. WLCSP는 웨이퍼 레벨에서 패키지 공정이 이루어진다는 특징으로 인하여 웨이퍼당 생산되는 반도체 칩의 수에 따라 그 패키징 비용을 크게 줄일 수 있다는 장점이 있다. 그러나 응력 버퍼 역할을 하는 기판을 없애는 혁신적인 구조로 인하여 솔더 조인트의 신뢰성이 기존의 BGA 패키지에 비하여 취약하게 되는데, 이러한 솔더 조인트 신뢰성에 대하여 반도체 칩과 솔더볼을 연결하는 폴리머 절연층은 열팽창계수 차이에 의해 발생하는 응력을 흡수하는 중요한 역할을 하게 된다. 본 연구에서는 하이닉스에서 개발한 Omega-CSP를 사용하여 솔더볼 배열 변화와 제 1 절연층의 특성에 따른 솔더 조인트의 열피로 특성을 평가하였다. 그 결과 절연층의 특성 변화가 솔더 조인트의 열피로 특성에 주는 영향은 솔더볼 배열 구조에 따라 변화되는 것을 확인하였다.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회A
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• pp.1673-1678
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• 2007

The use of flip-chip type electronic package offers numerous advantages such as reduced thickness, improved environmental compatibility, and downed cost. Despite numerous benefits, flip-chip type packages bare several reliability problems. The most critical issue among them is their electrical performance deterioration upon consecutive thermal cycles attributed to gradual delamination growth through chip and adhesive film interface induced by CTE mismatch driven shear and peel stresses. The electronic package in use is heated continuously by itself. When the crack at a weak site of the electronic package occurs, thermal deformationon the chip side is changed. Therefore, we can measure these micro deformations by using Moire interferometry and find out the crack length.

• 대한기계학회논문집A
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• 제33권4호
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• pp.380-387
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• 2009

The reliability concerns of solder interconnections in flip chip PBGA packages are produced mainly by the mismatch of coefficient of thermal expansion(CTE) between the module and PCB. Finite element analysis has been employed extensively to simulate thermal loading for solder joint reliability and deformation of packages in electronic packages. The objective of this paper is to study the thermo-mechanical behavior of FC-PBGA package assemblies subjected to temperature change, with an emphasis on the effect of the finite element model, material models and temperature conditions. Numerical results are compared with the experimental results by using $moir{\acute{e}}$ interferometry. Result shows that the bending displacements of the chip calculated by the finite element analysis with viscoplastic material model is in good agreement with those by $moir{\acute{e}}$ inteferometry.

• 마이크로전자및패키징학회지
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• 제21권2호
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• pp.23-29
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• 2014

Less power consumption, lower cost, smaller size and more functionality are the increasing demands for consumer electronic devices. The three dimensional(3-D) TSV packaging technology is the potential solution to meet this requirement because it can supply short vertical interconnects and high input/output(I/O) counts. Cu(Copper) has usually been chosen to fill the TSV because of its high conductivity, low cost and good compatibility with the multilayer interconnects process. However, the CTE mismatch and Cu ion drift under thermal stress can raise reliability issues. This study discribe the thermal stress reliability trend for successful implementation of 3-D packaging.

• 마이크로전자및패키징학회지
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• 제24권1호
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• pp.35-43
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• 2017

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.