• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.65-74
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• 2013

The through-silicon via (TSV) technology is essential for 3-dimensional integrated packaging. TSV technology, however, is still facing several reliability issues including interfacial delamination, crack generation and Cu protrusion. These reliability issues are attributed to themo-mechanical stress mainly caused by a large CTE mismatch between Cu via and surrounding Si. In this study, the thermo-mechanical reliability of copper TSV technology is investigated using numerical analysis. Finite element analysis (FEA) was conducted to analyze three dimensional distribution of the thermal stress and strain near the TSV and the silicon wafer. Several parametric studies were conducted, including the effect of via diameter, via-to-via spacing, and via density on TSV stress. In addition, effects of annealing temperature and via size on Cu protrusion were analyzed. To improve the reliability of the Cu TSV, small diameter via and less via density with proper via-to-via spacing were desirable. To reduce Cu protrusion, smaller via and lower fabrication temperature were recommended. These simulation results will help to understand the thermo-mechanical reliability issues, and provide the design guideline of TSV structure.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.101-105
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• 2019

The adhesion reliability of the epoxy molding compound (EMC) and the printed circuit board (PCB) interface is critical to the quality and lifetime of the chip package since the EMC protects PCB from the external environment during the manufacturing, storage, and shipping processes. It is necessary to measure adhesion energy accurately to ensure product reliability by optimizing the manufacturing process during the development phase. This research deals with the measurement of EMC/PCB interfacial adhesion energy of chip package that has warpage induced by the coefficient of thermal expansion (CTE) mismatch. The double cantilever beam (DCB) test was conducted to measure adhesion energy, and the spring back force of specimens with warpage was compensated to calculate adhesion energy since the DCB test requires flat substrates. The result was verified by comparing the adhesion energy of flat chip packages come from the same manufacturing process.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.7-15
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• 2012

Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.