• The Journal of the Acoustical Society of Korea
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• v.4 no.2
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• pp.36-47
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• 1985

본 논문에서는 기존의 ICE 기능을 갖춘 사용이 간편하고, 쉽게 이동이 가능한 저가격 범용 8비 트 마이크로프로세서의 실시간 에뮬레이터를 설계, 제작하고자 한다. ICE의 기능을 구현하기 위해서2개 의 보드 즉 에뮬레이션 보드와 콘트롤 보드를 사용하는 구조로 고안하였다. 에뮬레이션 보드에는 CPU 8085를 사용하고, 콘트롤 보드에는 표적시스템의 CPU와 같은 CPU를 사용하였다. 이러한 구조는 표적 CPU가 바뀔 때 콘트롤 보드만 교환하면 된다는 점에서 실용적이다. 에뮬레이션 보드는 범용 8비트 마 이크로프로세서에 대해서, 콘트롤 보드는 표적 CPU가 Z-80인 시스템에 대해서 제작하였다. 또한, 에뮬 레이터의 기능에 의해, 표적 CPU 자체의 기능이 상실됨을 회복시켰다.

• Journal of Korea Game Society
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• v.6 no.4
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• pp.55-61
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• 2006

Graphics rendering pipeline (application, geometry, and rasterizer) is the core of real-time graphics which is the most important functionality for computer games. Usually this rendering process is completed by both the CPU and the GPU, and a bottleneck can be located either in the CPU or the GPU. This paper focuses on reducing the bottleneck between the CPU and the GPU. We are proposing a method for improving the performance of parallel processing for real-time graphics rendering by separating the CPU operations (usually performed using a thread) into two parts: pure CPU operations and operations related to the GPU, and let them operate in parallel. This allows for maximizing the parallelism in processing the communication between the CPU and the GPU. Some experiments lead us to confirm that our method proposed in this paper can allow for faster graphics rendering. In addition to our method of using a dedicated thread for GPU related operations, we are also proposing an algorithm for balancing the graphics pipeline using the idle time due to the bottleneck. We have implemented the two methods proposed in this paper in our networked 3D game engine and verified that our methods are effective in real systems.

• Journal of Korea Multimedia Society
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• v.7 no.7
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• pp.886-895
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• 2004

In this paper, we propose the dynamic allocation scheme of the CPU bandwidth to efficiently integrate and schedule these tasks in the same system, where multimedia tasks and hard real-time tasks can coexist simultaneously. Hard real-time tasks are guaranteed based on worst case execution times, whereas multimedia tasks modeled as soft real-time tasks are served based on mean parameters. This paper describes a server-based allocation scheme for assigning the CPU resource to two types of tasks. Especially for MPEG video streams, we show how to dynamically control the fraction of the CPU bandwidth allocated to each multimedia task. The primary purpose of the proposed method is to minimize the mean tardiness of multimedia tasks while satisfying the timing constraints of hard real-time tasks present in the system. We showed through simulations that the tardiness experienced by multimedia tasks under the proposed allocation scheme is much smaller than that experienced by using other scheme.

• The KIPS Transactions:PartD
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• v.11D no.7 s.96
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• pp.1385-1398
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• 2004

This paper discusses an effective processing of subsequence matching under time warping in time-series databases. Time warping is a trans-formation that enables finding of sequences with similar patterns even when they are of different lengths. Through a preliminary experiment, we first point out that the performance bottleneck of Naive-Scan, a basic method for processing of subsequence matching under time warping, is on the CPU processing step. Then, we propose a novel method that optimizes the CPU processing step of Naive-Scan. The proposed method maximizes the CPU performance by eliminating all the redundant calculations occurring in computing the time warping distance between the query sequence and data subsequences. We formally prove the proposed method does not incur false dismissals and also is the optimal one for processing Naive-Scan. Also, we discuss the we discuss to apply the proposed method to the post-processing step of LB-Scan and ST-Filter, the previous methods for processing of subsequence matching under time warping. Then, we quantitatively verify the performance improvement ef-fects obtained by the proposed method via extensive experiments. The result shows that the performance of all the three previous methods im-proves by employing the proposed method. Especially, Naive-Scan, which is known to show the worst performance, performs much better than LB-Scan as well as ST-Filter in all cases when it employs the proposed method for CPU processing. This result is so meaningful in that the performance inversion among Nive- Scan, LB-Scan, and ST-Filter has occurred by optimizing the CPU processing step, which is their perform-ance bottleneck.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.1809-1815
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• 2008

This experiment simulated the fire driven flow of an underground station through parallel processing method. Fire analysis program FDS(Fire Dynamics Simulation), using LES(Large Eddy Simulation), has been used and a 6-node parallel cluster, each node with 3.0Ghz_2set installed, has been used for parallel computation. Simulation model was based on the Kwangju-geumnan subway station. Underground station, and the total time for simulation was set at 600s. First, the whole underground passage was divided to 1-Mesh and 8-Mesh in order to compare the parallel computation of a single CPU and Multi-CPU. With matrix numbers($15{\times}10^6$) more than what a single CPU can handle, fire driven flow from the center of the platform and the subway itself was analyzed. As a result, there seemed to be almost no difference between the single CPU's result and the Multi-CPU's ones. $3{\times}10^6$ grid point one employed to test the computing time with 2CPU and 7CPU computation were computable two times and fire times faster than 1CPU respectively. In this study it was confirmed that CPU could be overcome by using parallel computation.

• The Journal of the Korea Contents Association
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• v.8 no.12
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• pp.441-448
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• 2008

The molecular docking system needs a large amount of computation and requires super-computing power. Since the experiment requires a large amount of time, the experiment is conducted in the distributed environment or in the grid environment. Recently, researches on using parallel GPU of far higher performance than that of CPU in scientific computing have been very actively conducted. CUDA is an open technique by which a parallel GPU programming is made possible. This study proposes the molecular docking system using CUDA. It also proposes algorithm that parallels energy-minimizing-computation. To verify such experiments, this study conducted a comparative analysis on the time required for experimenting molecular docking in general CPU and the time and performance of the parallel GPU-based molecular docking which is proposed in this study.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.6
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• pp.353-359
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• 2016

In this paper, we propose a high performance L1 cache structure for the high clock CPU. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to reduce miss ratio, and a way-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is stored into the two-way set associative buffer. For the high performance and fast access time, we propose an one way among two ways set associative buffer is selectively accessed based on the way-select table (WST). According to simulation results, access time can be reduced by about 7% and 40% comparing with a direct cache and Intel i7-6700 with two times more space respectively.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.281-286
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• 2011

Data sorting is one of important pre-process to utilize huge data in modern society, but sorting spends a lot of time by sorting itself. In this paper, we presented hybrid sorting algorithm that splits array to sort concurrently in CPU and GPU. To do this, we decided most effective range of array based on hardware performance, then accomplished reducing whole sorting time by concurrent sorting on CPU and GPU. As shown in results of experiment, hybrid sorting improved about eight percent of sorting time in comparison with the sorting time using only GPU.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.6
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• pp.71-76
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• 2021

Recently, as the size of IoT data grows, the memory power consumption of real-time systems increases rapidly. This is because real-time systems always place entire tasks in memory, which increases the demand of DRAM significantly. In this paper, we adopt emerging fast storage media and move a certain portion of real-time tasks from DRAM to storage. The part of tasks in storage are, then, loaded into memory when they are actually used. We incorporate our memory/storage power-saving into the dynamic voltage/frequency scaling of processors, thereby optimizing power consumptions in CPU and memory simultaneously. Specifically, the proposed technique aims at minimizing the CPU idle time and the DRAM memory size by determining appropriate voltage modes of CPU and the swap ratio of memory, without violating the deadlines of all tasks. Through simulation experiments, we show that the proposed technique significantly reduces the power consumption of real-time systems.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.4
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• pp.43-49
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• 2021

A small infrared image homing system is a tracking system that has an infrared image sensor that identifies a target through the day and night infrared image processing of the target on the ground and searches for and detects the target with respect to the main target. This paper describes the development of a board equipped with a high-speed CPU and FPGA (Field Programmable Gate Array) to identify target through real-time image processing by acquiring target information through infrared image. We propose a CPU-FPGA combining architecture for CPU and FPGA selection and video signal processing, and also describe a controller design using FPGA to control infrared sensor.