• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.5
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• pp.162-167
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• 1994

The binary image normalization method in image processing can be used in several fields, Especially, its high speed processing method and its hardware implmentation is more useful, A normalization process of each character in character recognition requires a lot of processing time. Therefore, the research was done as a part of high speed process of OCR (optical character reader) implementation as a pipeline structure with host computer in hardware to give temporal parallism. For normalization process, general purpose CPU,MC68000, was used to implement it. As a result of experiment, the normalization speed of the hardware is sufficient to implement high speed OCR which the recognition speed is over 140 characters per second.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.671-672
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• 2006

Recently Communication with using IrDA is bing used in various fields. In this paper I designed a receiver by fabricating hardware that used to be fabricated through software, so anyone who don't have knowledge on IrDA can receive Ir Signal easily. This receiver can communicate with CPU through 8 bit data and 3 bit address. Also this receiver can use user-needed CLK because this receiver embodied 16 bit CLK Prescaler.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.80-87
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• 1993

In this paper, the fields of double-plane steps in rectangular waveduides are analyzed using the modified TE$_{mn}$$^{x}$ mode-matching method. The characteristics of rectangular waveguide having double-plane steps are investigated with accomdating the effects of higher-order modes generated by discontinuities. In comparison with the generalized TE$_{mn}$-TM$_{mn}$ mode analysis, the modified TE$_{mn}$$^{x}$ mode-matching method consumes less memory and CPU time and provides improved convergence behavior. The results obtained in this manner coinside with that of the TE$_{mn}$-TM$_{mn}$ mode-matching method.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.7
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• pp.594-601
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• 2000

EIA-709.1 Control Network Protocol is the basic protocol of LonWorks systems that is emerg-ing as a fieldbus device. In this paper the protocol is implemented by using VHDL with FPGA and C program on an Intel 8051 processor. The protocol from the physical layer to the network layer of EIA-709.1 is im-plemented in a hardware level,. So it decreases the load of the CPU for implementing the protocol. We verify the commercial feasibility of the hardware through the communication test with Neuron Chip. based on EIA-709.1 protocol which is used in industrial fields. The developed protocol based on FPGA becomes one of IP can be applicable to various industrial field because it is implemented by VHDL.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1189-1192
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• 1996

In this paper, a fault diagnosis method is proposed for self-diagnostics of PLC(Programmable Logic Controller), process controller in industrial fields, and diagnosis of its external devices such as sensors and actuators. The aim of this research is proposition of systematic method of fault diagnosis of PLC control system and development of its equipment. A PLC fault diagnosis algorithm consists of self-diagnostics given by PLC makers, Inpuot/Output tracking method by analyzing sequence PLC programs, searching method of past fault cases in database using an expert system, and diagnosis of PLC units such as CPU, DI, and DO board. Finally usability of PLC fault diagnostic system is verified by testing a MELSEC PLC.

• Journal of Information Processing Systems
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• v.14 no.6
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• pp.1301-1306
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• 2018

Artificial intelligence is one of the key technologies of the Fourth Industrial Revolution. This paper introduces the diverse kinds of approaches to subjects that tackle diverse kinds of research fields such as model-based MS approach, deep neural network model, image edge detection approach, cross-layer optimization model, LSSVM approach, screen design approach, CPU-GPU hybrid approach and so on. The research on Superintelligence and superconnection for IoT and big data is also described such as 'superintelligence-based systems and infrastructures', 'superconnection-based IoT and big data systems', 'analysis of IoT-based data and big data', 'infrastructure design for IoT and big data', 'artificial intelligence applications', and 'superconnection-based IoT devices'.

• Journal of the Semiconductor & Display Technology
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• v.22 no.2
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• pp.128-132
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• 2023

Recently, with the development of deep learning technology, research on pedestrian attribute recognition technology using deep neural networks has been actively conducted. Existing pedestrian attribute recognition techniques can be obtained in such a way as global-based, regional-area-based, visual attention-based, sequential prediction-based, and newly designed loss function-based, depending on how pedestrian attributes are detected. It is known that the performance of these pedestrian attribute recognition technologies varies greatly depending on the type of backbone network that constitutes the deep neural networks model. Therefore, in this paper, several backbone networks are applied to the baseline pedestrian attribute recognition model and the performance changes of the model are analyzed. In this paper, the analysis is conducted using Resnet34, Resnet50, Resnet101, Swin-tiny, and Swinv2-tiny, which are representative backbone networks used in the fields of image classification, object detection, etc. Furthermore, this paper analyzes the change in time complexity when inferencing each backbone network using a CPU and a GPU.

• Journal of KIISE
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• v.44 no.5
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• pp.537-544
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• 2017

As a special form of the signed-digit representation, the NAF(non-adjacent form) minimizes the hamming weight by reducing the average density of the non-zero bits from the binary representation of the positive integer k. Due to this advantage, the NAF is used in various fields; in particular, it is actively used in cryptology. The existing NAF-conversion algorithm, however, is problematic because the conversion speed decreases when the LSB(least significant bit) frequently becomes "1" during the binary positive integer conversion process. This paper suggests a method for the improvement of the NAF-conversion speed for which the problems that occur in the existing NAF-conversion process are solved. To verify the performance improvement of the algorithm, the CPU cycle for the various inputs were measured on the ATmega128, a low-performance 8-bit microprocessor. The results of this study show that, compared with the existing algorithm, the suggested algorithm not only improved the processing speed of the major patterns by 20% or more on average, but it also reduced the NAF-conversion time by 13% or more.

• Journal of Digital Contents Society
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• v.18 no.6
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• pp.1165-1173
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• 2017

Deep learning method, which is one of the most famous machine learning algorithms, has proven its applicability in various applications and is widely used in digital signal processing. However, it is difficult to apply deep learning technology to IoT devices with limited CPU performance and memory capacity, because a large number of training samples requires a lot of memory and computation time. In particular, if the Arduino with a very small memory capacity of 2K to 8K, is used, there are many limitations in implementing the algorithm. In this paper, we propose a method to optimize the ELM algorithm, which is proved to be accurate and efficient in various fields, on Arduino board. Experiments have shown that multi-class learning is possible up to 15-dimensional data on Arduino UNO with memory capacity of 2KB and possible up to 42-dimensional data on Arduino MEGA with memory capacity of 8KB. To evaluate the experiment, we proved the effectiveness of the proposed algorithm using the data sets generated using gaussian mixture modeling and the public UCI data sets.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.26-36
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• 1999

In this paper, the novel scheme of OAM performance management function is proposed to supply the most of network resources and reliable services by processing data having various QoS(quality of service) in the view of cell loss and cell delay of ATM networks Also, the special fields of OAM cell are defined in order to improve correlate control, operation, and management technique between networks which is required to flexibility and precision control as detecting the performance information of the variable networks periodically. The proposed OAM function, the input/output function of cell, and the interface function of the accessory device which is likely to the memory/CPU are designed to ASIC. The designed chip is carried out the back-end simulation using Verilog-XL simulator of Cadence. In result, it is able to performs an accurate control in $2{\mu}s$.