• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12A
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• pp.2027-2035
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• 2001

In this paper, we present an audio stream delivery using the AMR (Adaptive Multi-Rate) coder that was adopted by ETSI and 3GPP as a standard vocoder for next generation IMT-2000 service in which includes combined sender (FEC) and receiver reconstruction technique in the Internet. By use of the media-specific FEC scheme, the possibility to recover lost packets can be much increased due to the addition of repair data to a main data stream, by which the contents of lost packets can be recovered. The AMR codec is based on the code-excited linear predictive (CELP) coding model. So we use a frame erasure concealment for CELP-based coders. The proposed scheme is evaluated with ITU-T G.729 (CS-ACELP) coder and AMR - 12.2 kbit/s through the SNR (Signal to Noise Ratio) and the MOS (Mean Opinion Score) test. The proposed scheme provides 1.1 higher in Mean Opinion Score value and 5.61 dB higher than AMR - 12.2 kbit/s in terms of SNR in 10% packet loss, and maintains the communicab1e quality speech at frame erasure rates lop to 20%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6A
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• pp.618-627
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• 2002

In processing images using 2 dimensional Discrete Wavelet Transform(2D-DWT), the method to process the pixels around the image boundary may affect the quality of image and the cost to implement in hardware and software. This paper proposed an effective method to treat the boundary pixels, which is apt to implement in hardware and software without losing the quality of the image costly. This method processes the 2-D image as 1-D array so that 2-D DWT is performed by considering the image with the serial-sequential data structure (Serial-Sequential Processing). To show the performance and easiness in implementation of the proposed method, an image compression codec which compresses image and reconstructs it has been implemented and experimented. It included log-scale fried quantizer, but the entropy coder was not implemented. From the experimental results, the proposed method showed the SNR of almost the same SNR(Signal to Noise Ratio) to the Periodic Expansion(PE) method when the compression ratio(excluding entropy coding) of 2:1, 15.3% higher than Symmetric Expansion(SE) method, and 9.3% higher than 0-pixel Padding Expansion(ZPE) method. Also PE method needed 12.99% more memory space than the proposed method. By considering only the compression process, SE and ZPE methods needed additional operations than the proposed one. In hardware implementation, the proposed method in this paper had 5.92% of overall circuit as the control circuit, while SE, PE, and ZPE method has 22%, 21,2%, and 11.9% as the control circuit, respectively. Consequently, the proposed method can be thought more effective in implementing software and hardware without losing any image quality in the usual image processing applications.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.153-164
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• 2010

A program consumes energy by executing its instructions. The amount of cosumed power is mainly proportional to algorithm complexity and it can be calculated by using complexity information. Generally, the complexity of a S/W is estimated by the microprocessor simulator. But, the simulation takes long time why the simulator is a software modeled the hardware and it only provides the information about computational complexity quantitatively. In this paper, we propose a complexity estimation method of analysis of S/W on source code level and produce the complexity metric mathematically. The function-wise complexity metrics give the detailed information about the calculation-concentrated location in function. The performance of the proposed method is compared with the result of the gate-level microprocessor simulator 'SimpleScalar'. The used softwares for performance test are $4{\times}4$ integer transform, intra-prediction and motion estimation in the latest video codec, H.264/AVC. The number of executed instructions are used to estimate quantitatively and it appears about 11.6%, 9.6% and 3.5% of error respectively in contradistinction to the result of SimpleScalar.

• Journal of Broadcast Engineering
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• v.25 no.3
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• pp.346-352
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• 2020

Versatile Video Coding (VVC), a next-generation video coding standard that is in the final stage of standardization, has adopted various techniques to achieve more than twice the compression performance of HEVC (High-Efficiency Video Coding). VVC adopted Bi-prediction with CU-level Weight (BCW), which generates the final prediction signal with the weighted combination of bi-predictions with various weights, to enhance the performance of the bi-predictive inter prediction. The syntax element of the BCW index is adaptively coded according to the value of NoBackwardPredFlag which indicates if there is no future picture in the display order among the reference pictures. Such syntax structure for signaling the BCW index could violate the flexibility of video codec and cause the dependency issue at the stage of bitstream parsing. To address these issues, this paper proposes an efficient BCW weight signaling method which enables all weights and parsing without any condition check. The performance of the proposed method was evaluated with various weight searching methods in the encoder. The experimental results show that the proposed method gives negligible BD-rate losses and minor gains for 3 weights searching and 5 weights searching, respectively, while resolving the issues.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.397-409
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• 2003

This paper describes an implementation of radix-4 trellis parallel architecture and backward state transition control trace back Viterbi decoder, and presents the application results to high speed wireless LAN. The radix-4 parallelized architecture Vietrbi decoder can not only improve the throughput with simple structure, but also have small processing delay time and overhead circuit compared to M-step trellis architecture one. Based on these features, this paper addresses a novel Viterbi decoder which is composed of branch metric computation, architecture of ACS and trace back decoding by sequential control of backward state transition for the implementation of radix-4 trellis parallelized structure. With the proposed architecture, the decoding of variable code rate due to puncturing the base code can easily be implemented by the unified Viterbi decoder. Moreover, any additional circuit and/or peripheral control logic are not required in the proposed decoder architecture. The trace back decoding scheme with backward state transition control can carry out the sequential decoding according to ACS cycle clock without additional circuit for survivor memory control. In order to evaluate the usefulness, the proposed method is applied to channel CODEC of the IEEE 802.11a high speed wireless LAN, and HDL coding simulation results are presented.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.989-992
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• 1999

Battery로 작동되고, 소형인 제품들도 다양한 기능은 물론이고, 다양한 입출력 장치를 갖추고, 실시간으로 처리하는 시스템이 많이 요구되고 있는 실정이며, 점차 더욱 더 요구될 것으로 전망된다. 더욱이 포터블 기기는 일반적으로 MCU의 내부에 제한된 ROM type 메모리를 내장하게 되면, 데이터 메모리로 SRAM 및 flash memory를 갗추고 있다. 따라서 이러한 제한된 하드웨어 환경하에서 많은 기능을 수행해야 하는 경우가 많다. 여러 기능을 시간적인 간격으로 배분하거나, 기능 자체를 서로 배분하면서, 서로 융합하는 등의 여러 가지 기능을 수행하려다보면, 당연히 메인 소프트웨어 구조가 복잡해지며 대부분 어셈블리나 C와 같은 linear한 구조를 가지는 language로 개발되기 때문에 효과적인 프로그램 구조를 세우기는 쉽지 않다. 본 논문에서는 이를 위해 좀더 규격화된 방법을 제시하고자 한다. 보다 구체적인 구조를 연구할 목적으로 다양한 테스크를 수행하여야 하는 시스템이면서 프로세서가 필요한 포터블 기기의 한 응용 제품인 MP3 Player 에서 요구되는 job scheduling을 연구한다. 필요한 작업의 종류는 가장 부하가 많이 걸리는 압축된 MP3 file을 다시 복원시켜주는 codec 부분과 일정 시간 간격을 가지고 수행하여야 하는 외부 키보드 입력과 실시간으로 시간을 계산하는 타이머 기능, 그리고 LCD에 시간의 변화를 표시하여 주어야한다. 이와같이 수시로 작업이 발생하지만 시간 점유율이 중간 정도인 LCD 컨트롤과 메모리 컨트롤 등이다. 프로세서의 속도를 최소한으로 줄이면서 스케줄링에 의해 시간 문제를 해결하는 방법을 제시하도록 한다. 이는 기초과학 수준이 높은 북방권 국가들의 과학자들이 주로 활용되고 있다는 점에서도 잘 알 수 있으며 우리의 과학기술 약점을 보완하는 원천으로써 외국인 연구 인력이 대안이 되고 있음을 시사한다. 본 연구에서는 한국 연구 조직에서 일하는 외국인 연구자들의 동기 및 성과에 영향을 미치는 많은 요인들을 확인할 수 있었다. 상관관계, 분산분석, 회귀분석 등을 통해 활용 성과에 미치는 영향 요인들을 도출하였다. 설문 분석을 통하여 동기 및 성과 사이에는 강한 상관관계가 존재하는 것을 확인할 수 있었으며 이는 전통적인 동기 이론들과 부합한다. 대부분의 변수가 동기 및 성과에 동시에 영향을 미치는 것으로 조사되었으며 그중에서도 조직 협력 문화, 외국인 연구자의 의사소통 및 협력성, 외국인 연구자의 연구 능력 관련 변수들 및 연구 프로젝트의 기술수명주기, 외국인 연구자의 기존 기술지식의 흡수 등이 가장 중요한 변수로 나타났다. 이는 우리가 주로 중국 및 러시아 과학자들을 활용하여 상업화하는 외국인 연구인력 활용 패턴과도 일치하는 결과이다. 즉 우호적인 조직문화를 가지고 있는 연구 조직에서, 이미 과학기술 지식을 많이 가지고 있고 연구 능력도 높은 외국인 과학기술자를, 한국에서 기술이 태동 또는 성장하고 있는 연구 분야에서 활용하는 것이 가장 성과가 좋다는 사실을 확인시켜 주고 있다. 국내에서 최초로 수행된 본 연구는 외국인 연구 인력의 활용 성과가 매우 높으며, 우리의 과학기술혁신시스템을 보완하는 유효한 수단으로써 외국인 연구 인력이 중요한 대안이 될 수 있음을 발견하였다. 외국인 연구 인력을 잘 활용하기 위하여 문제점 및 개선방안을 활용 환경, 연구 인력이 중요한 대안이 될 수

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.116-126
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• 2011

In this paper, we present a multi-media processor which can decode multiple-format video standards. The designed processor is evaluated with optimized MPEG-2, MPEG-4, and AVS (Audio video standard). There are two approaches for developing of real-time video decoders. First, hardware-based system is much superior to a processor-based one in execution time. However, it takes long time to implement and modify hardware systems. On the contrary, the software-based video codecs can be easily implemented and flexible, however, their performance is not so good for real-time applications. In this paper, in order to exploit benefits related to two approaches, we designed a processor called ASIP(Application specific instruction-set processor) for video decoding. In our work, we extracted eight common modules from various video decoders, and added several multimedia instructions to the processor. The developed processor for video decoders is evaluated with the Synopsys platform simulator and a FPGA board. In our experiment, we can achieve about 37% time saving in total decoding time.

• Journal of Broadcast Engineering
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• v.15 no.5
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• pp.653-664
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• 2010

Generally existing video codec employs entropy coding to deal with residual signals with considering temporal and spatial properties. Scalable Video Coding(SVC) which is extension of H.264/AVC has three technical concepts for removing redundancies between inter-layers. In spite of using novel prediction method between inter-layers in SVC, it is still using same entropy coding method to residual signals. According to the studies, the residual obtained by inter-layer prediction technique has different features of residual signal acquired by spatial or temporal prediction technique. In this paper, we propose an efficient entropy coding method which codes the residual signal obtained by inter-layer prediction with regarding its features adequately. We re-designed the Coded Block Pattern(CBP) table suitably for inter-layer texture prediction. The experiments show that the proposed method can further reduce the BD-Bitrate up to average 2.20% in 4CIF and 1.14% in CIF resolution compared to the existing JSVM 9.18.

• Journal of Broadcast Engineering
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• v.15 no.3
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• pp.380-390
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• 2010

The most recent standard video codec, H.264/AVC achieves significant coding efficiency by using a rate-distortion optimization(RDO). The RDO is a measurement for selecting the best mode which minimizes the Lagrangian cost among several modes. As a result, the computational complexity is increased drastically in encoder. In this paper, a method for fast intra prediction mode decision is proposed to reduce the RDO complexity. To speed up Intra$4{\times}4$ and Chroma Intra encoding, the proposed method decides the case that MPM (Most Probable Mode) is the best prediction mode. In this case, the RDO process is skipped, and only MPM is used for encoding the block in Intra$4{\times}4$. And the proposed method is also applied to the chroma Intra prediction mode in a similar way to the Intra$4{\times}4$. The experimental results show that the proposed method achieves an average encoding time saving of about 63% with negligible loss of PSNR (Peak Signal-to-Noise Ratio).