• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.93-96
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and nonuniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between partical size and CMP with partical size analysis of used slurry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.184-187
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) lyaer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2-CMP$ process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and nonuniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between partical size and CMP with partical size analysis or used slurry.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.4
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• pp.325-331
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• 2007

In this study, the inter-metal dielectric material of FSG was changed by low-k material in $0.13{\mu}m$ foundry-compatible technology (FCT) device process based on fluorinated silicate glass (FSG). Black diamond (BD) was used as a low-k material with a dielectric constant of 2.95 for optimization and yield-improvement of the low-k based device process. For yield-improvement in low-k based device process, some problems such as photoresist (PR) poisoning, damage of low-k in etch/ash/cleaning process, and chemical mechanical planarization (CMP) delamination must be solved. The PR poisoning was not observed in BD based device. The pressure in CMP process decreased to 2.8 psi to remove the CMP delamination for Cu-CMP and USG-CMP. $H_2O$ ashing process was selected instead of $O_2$ ashing process due to the lowest condition of low-k damage. NE14 cleaning after ashing process lot the removal of organic residues in vias and trenches was employed for wet process instead of dilute HF (DHF) process. The similar-state of SRAM yield was obtained in Cu/low-k process compared with the conventional $0.13{\mu}m$ FCT device by the optimization of these process conditions.

• Tribology and Lubricants
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• v.33 no.6
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• pp.282-287
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• 2017

SU-8 is an epoxy-type photoresist widely used for the fabrication of high-aspect-ratio (HAR) micro-structures in micro-electro-mechanical systems (MEMS). To fabricate highly integrated structures, chemical mechanical polishing (CMP) has emerged as the preferred manufacturing process for planarizing the MEMS structure. In SU-8 CMP, an oxidizer decomposes organic impurities and particles in the CMP slurry remove the chemically reacted surface of SU-8. To fabricate HAR microstructures using the CMP process, the adhesion between SU-8 and substrate material is important to avoid the delamination of the SU-8 film caused by the mechanical-dominant material removal characteristic. In this study, the friction force during the CMP process is measured with a CMP monitoring system to detect the delamination phenomenon and investigate the delamination of the SU-8 film from the silicon substrate under various pressure conditions. The increase in applied pressure causes an increase in the frictional force and wafer-edge stress concentration. The frictional force measurement shows that the friction force changes according to the delamination phenomenon of the SU-8 film, and that it is possible to monitor the delamination phenomenon during the SU-8 CMP process. The delamination at a high applied pressure is explained by the effect of stress distribution and pad deformation. Consequently, it is necessary to control the pressure of polishing, which can avoid the delamination in SU-8 CMP.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1181-1186
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• 2003

Chemical Mechanical Polishing (CMP) is an essential dielectric planarization in multilayer microelectronic device fabrication. In the CMP process, it is necessary to minimize the extent of surface defect formation while maintaining good planarity and optimal material removal rates. The polishing mechanism of W-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. Thus, it is important to understand the effect of oxidizer on W passivation layer, in order to obtain higher removal rate (RR) and very low non-uniformity (NU %) during W-CMP process. In this paper, we compared the effects of oxidizer or W-CMP process with three different kind of oxidizers with 5 wt% hydrogen peroxide such as Fe(NO$_3$)$_3$, H$_2$O$_2$, and KIO$_3$. The difference in removal rate and roughness of W in stable and unstable slurries are believed to caused by modification in the mechanical behavior of Al$_2$O$_3$ particles in presence of surfactant stabilizing the slurry.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.1283-1288
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• 2003

The friction heat generated by the CMP process hasinfluence on removal rate and WIWNU(Within Wafer Non-Uniformity). Therefore, the object of this study is to find the distribution of temperature on pad surface during CMP process. To do this, the authors analyse the kinematics of CMP equipment to verify the sources of friction heat and compare the analysis result with the experimental results. Through the analysis and experiment conducted in this paper, we can predict the distribution of polishing temperature across the pad surface. Furthermore the result could help to predict the process conditions which could enhance the polishing results, such as WIWNU and removal rate of thin film to achieve more efficient process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.178-181
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• 2002

We studied the characteristics of polishing pad, which can apply W CMP process for global planarization of multilevel interconnection structure. Also we investigated the effects of different sets of polishing pad. The purpose of this experiment is the cost reduction by the increase of pad life time and decrease of cycle time and slurry usage with new pad. Especially we studied the effect of polishing pad for CMP process by this experiment of polishing pad that is consumables material during CMP process. We expecting the increase of process throughput and improvement of device manufacturing yield because we can choose optimum polishing pad through this result.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.501-504
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• 1999

In the shallow trench isolation(STI) chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control within- wafer-non-uniformity, and the possible defects such as nitride residue and pad oxide damage. These defects after STI CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI filling and STI CMP were discussed. It is represented that the nitride residue can be occurred in the condition of high post CMP thickness and low trench depth. In addition there are remaining oxide on the moat surface after reverse moat etch. It means that reverse moat etching process can be the main source of nitride residue. Pad oxide damage can be caused by over-polishing and high trench depth.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.228-232
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• 2002

The rise throughput and the stability in the device fabrication can be obtained by applying chemical mechanical polishing(CMP) process in 0.18 ${\mu}m$ semiconductor device. However it does have various problems due to the CMP equipment. Especially, among the CMP components, process variables are very important parameters in determining removal rate and non-uniformity. In this paper, We studied the DOE(design of experiment) method for the optimized CMP process. Various process variations, such as table and head speed, slurry flow rate and down force, have investigated in the viewpoint of removal rate and non-uniformity. Through the above DOE results, we could set-up the optimal process parameters.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.51-54
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• 2006

본 연구는 CMP 공정 중의 Conditioning 최적화에 관한 내용이다. CMP Pad Conditioner의 역할은 CMP 공정 중 Slurry 및 연마 잔유물에 의해 Pad 표면에 눈막힘 현상(Glazing)이 발생하여 Wafer의 연마속도가 급속히 저하되는 현상을 방지하여 공정의 안정성을 향상시키는 데 있다. 본 연구 중 Conditioning은 In-situ 방식으로 진행되었으며, Conditioning 비율을 Polishing Time 대비 50%만 진행하여도 연마속도 저하현상은 나타나지 않음을 확인하였다. 이로써 Pad 마모랑 감소 및 Conditioner 교체 주기연장이 가능해져, CMP 공정의 Cost를 절감할 수 있다.