• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.05a
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• pp.239-239
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• 2004

화학적 기계연마 공정(CMP)은 반도체 웨이퍼를 수 천$\AA$m/min의 MRR로 2$\mu\textrm{m}$ 이내의 W(Total Thickness Variable) 조건을 만족시키는 초정밀 광역 평탄화 기술이다. 일반적인 CMP 방법은 서로 다른 회전 중심을 갖고 동일한 방향으로 회전하는 웨이퍼와 다공성 패드 사이에 연마액인 슬러리를 넣어 연마하는 것이다. CMP 공정기술은 1990년 대 중반에 개발되었으나, 아직까지 연마 메커니즘이 완벽하게 밝혀지지 않았다. 따라서 장비를 최적화하기 위해 실험에 의존적일 수밖에 없으나, 이러한 방법은 막대한 자금과 노력뿐만 아니라 상당한 시간을 필요로 하기 때문에, 앞으로 가속될 연마대상 재료의 변화 및 다양한 속도에 발맞출 수 없다.(중략)

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1271-1272
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• 2006

CMP(chemical mechanical polishing) process has been attracted as an essential technology of multi-level interconnection. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, slurry dominates more than 40%. So, we focused how to reduce the consumption of raw slurry. In this paper, $ZrO_2$, $CeO_2$, and $MnO_2$ abrasives were added de-ionized water (DIW) and pH control as a function of KOH contents. We have investigate the possibility of new abrasive for the oxide CMP application.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.81-82
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• 2006

Chemical mechanical polishing (CMP) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, the cost of ownership and cost of consumables are relatively high because of expensive slurry. In this paper, so as to investigate the influence of mixed abrasive slurry (MAS), such as $ZrO_2$, $CeO_2$, and $MnO_2$ for Ti-CMP application.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.107-108
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• 2006

In this work, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. $Bi_{3.25}La_{0.75}Ti_{3}O_{12}$ (BLT) ferroelectric film was fabricated by the sol-gel method. However, there have been serious problems in CMP in terms of repeatability and defects in patterned wafer. Especially, dishing & erosion defects increase the resistance because they decrease the interconnect section area, and ultimately reduce the lifetime of the semiconductor. Cross-sections of the wafer before and after CMP were examined by Scanning electron microscope(SEM). Process characteristics of non-dishing and erosion were investigated.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1731-1732
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• 2006

CMP(chemical mechanical polishing) process has been attracted as an essential technology of multi-level interconnection. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, slurry dominates more than 40 %. So, we focused how to reduce the consumption of raw slurry. In this paper, $ZrO_2$, $CeO_2$, and $MnO_2$ abrasives were added de-ionized water (DIW) and pH control as a function of KOH contents. We have investigate the possibility of new abrasive for the oxide CMP application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.149-153
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• 2003

Chemical mechanical polishing (CMP) technology for global planarization of multi-level inter-connection structure has been widely studied for the next generation devices. CMP process has been paid attention to planarized pre-metal dielectric (PMD), inter-layer dielectric (ILD) interconnections. Expecially, shallow trench isolation (STI) used to CMP process on essential. Recently, the direct STI-CMP process without the conventional complex reverse moat etch process has established by using slurry additive with the high selectivity between $SiO_2$ and $Si_3N_4$ films for the purpose of process simplification and n-situ end point detection(EPD). However, STI-CMP process has various defects such as nitride residue, tom oxide and damage of silicon active region. To solve these problems, in this paper, we studied the planarization characteristics using a high selectivity slurry(HSS). As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of HSS STI-CMP process.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.28 no.1
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• pp.51-56
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• 2018

To evaluate surface characteristics of AlN single crystal grown by physical vapor transport (PVT) method, chemical mechanical polishing (CMP) were performed with diamond slurry and $SiO_2$ slurry after mechanical polishing (MP), then the surface morphology and analysis of polishing characteristics of the slurry types were analyzed. To estimate how pH of slurry effects polishing process, pH of $SiO_2$ slurry was controlled, the results from estimating the effect of zeta potential and MRR (material removal rate) were compared in accordance with each pH via zeta potential analyzer. Eventually, surface roughness RMS (0.2 nm) could be derived with atomic force microscope (AFM).

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.319-325
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• 2017

Through silicon via (TSV) technology is extensively used in 3D IC integrations. The special structure of the TSV is realized by CMP (Chemically Mechanical Polishing) process with a high Cu removal rate and, low dishing, yielding fine topography without defects. In this study, we investigated the electrochemical behavior of copper slurries with various inhibitors in the Cu CMP process for advanced TSV applications. One of the slurries was carried out for the most promising process with a high removal rate (${\sim}18000{\AA}/Min$ @ 3 psi) and low dishing (${\sim}800{\AA}$), providing good microstructure. The effects of pH value and $H_2O_2$ concentration on the slurry corrosion potential and Cu static etching rate (SER) were also examined. The slurry formula with a pH of 6 and 2% $H_2O_2$, hadthe lowest SER (${\sim}75{\AA}/Min$) and was the best for TSV CMP. A novel Cu TSV CMP process was developed with two CMPs and an additional annealing step after some of the bulk Cu had been removed, effectively improving the condition of the TSV Cu surface and preventing the formation of crack defects by variations in wafer stress during TSV process integration.

• Journal of the Korean Vacuum Society
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• v.11 no.4
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• pp.235-239
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• 2002

A new method for deep trench isolation using selective growth of polycrystalline silicon is proposed. In this method, trench filling is performed by forming polysilicon-inner sidewalls within the trench, and then selectively growing them by reduced chemical vapor deposition using $SiH_2C1_2$gas at $1100^{\circ}C$. The surface profiles of filled trenches are determined mainly by the initial depth of inner sidewalls and the total thickness of selective growth. No chemical mechanical polishing(CMP) process is needed in this new method, which makes the process flow simpler and more reliable in comparison with the conventional method using CMP process.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2008.05a
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• pp.7-9
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• 2008

ITO thin film is generally fabricated by various. methods such as spray, CVD, evaporation, electron gun deposition, direct current electroplating, high frequency sputtering, and reactive DC sputtering. However, some problems such as peaks, bumps, large particles, and pin-holes on the surface of ITO thin film were reported, which caused the destruction of color quality, the reduction of device life time, and short-circuit. Chemical mechanical polishing (CMP) process is one of the suitable solutions which could solve the problems