• 센서학회지
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• 제30권5호
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• pp.295-299
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• 2021

In this study, we present a complementary metal-oxide-semiconductor (CMOS) binary image sensor. It can shoot an object rotating at a high-speed by using a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector. The GBT PMOSFET-type photodetector amplifies the photocurrent generated by light. Therefore, it is more sensitive than a standard N+/P-substrate photodetector. A binary operation is installed in a GBT PMOSFET-type photodetector with high-sensitivity characteristics, and the high-speed operation is verified by the output image. The binary operations circuit comprise a comparator and memory of 1- bit. Thus, the binary CMOS image sensor does not require an additional analog-to-digital converter. The binary CMOS image sensor is manufactured using a standard CMOS process, and its high- speed operation is verified experimentally.

• 센서학회지
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• 제30권2호
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• pp.82-87
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• 2021

In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.98-101
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• 2007

A fully integrated 5-GHz CMOS power amplifier for IEEE 802.11a WLAN applications is implemented using $0.18-{\mu}m$ CMOS technology. An on-chip transmission-line transformer is used for output matching network and voltage combining. Input balun, inter-stage matching components, output transmission line transformer and RF chokes are fully integrated in the designed amplifier so that no external components are required. The power amplifier occupies a total area of $1.7mm{\times}1.2mm$. At a 3.3-V supply voltage, the amplifier exhibits a 22.6-dBm output 1-dB compression point, 23.8-dBm saturated output power, 25-dB power gain. The measured power added efficiency (PAE) is 20.1 % at max. peak, 18.8% at P1dB. When 54 Mbps/64 QAM OFDM signal is applied, the PA delivers 12dBm of average power at the EVM of -25dB.

• ETRI Journal
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• 제36권1호
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• pp.141-150
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• 2014

A fully integrated CMOS security-enhanced passive (SEP) tag that compensates the security weakness of ISO/IEC 18000-6C is presented in this paper. For this purpose, we propose a security-enhanced protocol that provides mutual authentication between tag and reader. We show that the proposed protocol meets the security demands of the ongoing international standard for RFID secure systems, ISO/IEC 29167-6. This paper fabricates the SEP tag with a 0.18-${\mu}m$ CMOS technology and suggests the optimal operating frequency of the CMOS SEP tag to comply with ISO/IEC 18000-6C. Furthermore, we measure the SEP tag under a wireless environment. The measured results show that communications between the SEP tag and reader are successfully executed in both conventional passive and SEP modes, which follow ISO/IEC 18000-6C and the proposed security enhanced protocol, respectively. In particular, this paper shows that the SEP tag satisfies the timing link requirement specified in ISO/IEC 18000-6C.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 D
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• pp.2577-2579
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• 2002

In this paper, we describe a CMOS DC-DC converter with a variable output voltage(8-12V @100mA) for a portable battery-operated system applications. The proposed DC-DC converter is used along with a Pulse-Frequency Modulation (PFM) method and consists of a reference circuit, a feedback resistor, a controller, and an internal oscillator. The integrated DC-DC converter with two external passive components(L.C) has been designed and fabricated on a 0.6${\mu}m$ 2-poly, 3-metal CMOS process and could be applied to the Personal Digital Assistants(PDA), Cellular Phone, Laptop Computer, etc.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.14-21
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• 2009

A digital differential transmitter based on CMOS inverter worked up to 2.8 Gbps at the supply voltage of 1 V with a $0.18{\mu}m$ CMOS process. By calibrating the output impedance of the transmitter, the impedance matching between the transmitter output and the transmission line is achieved. The PVT variations of pre-driver are compensated by the calibration of the rising-edge delay and falling-edge delay of the pre-driver outputs. The chip fabricated with a $0.18{\mu}m$ CMOS process, which uses the standard supply voltage of 1.8 V, gives the highest data rate of 4Gbps at the supply voltage of 1.2 V. The proposed calibration schemes improve the eye opening with the voltage margin by 200% and the timing margin by 30%, at 2.8 Gbps and 1 V.

• 대한전자공학회논문지SD
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• 제45권4호
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• pp.131-136
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• 2008

[ $0.18-{\mu}m$ ] CMOS공정을 이용하여 근거리 무선통신(22-29 GHz)에서 응용할 수 있는 전력증폭기를 설계하였다. 전도성 기판에 의한 손실을 줄이기 위해서 기판 차폐된 두 가지 형태의 전송선로를 설계하고, 40 GHz 까지 측정 및 모델링하였다. 기판 차폐 microstrip line (MSL) 전송선로의 경우 27 GHz에서 약 0.5 dB/mm의 삽입손실을 나타내었다. 기판 차폐 MSL 구조를 이용한 전력증폭기는 0.83$mm^2$의 비교적 작은 면적을 차지하면서도 27 GHz에서 14.7 dB의 소신호 이득과 14.5 dBm의 출력을 나타내었다. 기판 차폐 coplanar waveguide (CPW) 전송선로의 경우 27 GHz에서 약 1.0 dB/mm 삽입손실을 나타내었으며, 이를 이용한 전력증폭기는 26.5 GHz에서 12 dB의 소신호 이득과 12.5 dBm의 출력을 나타내었다. 본 논문의 결과는 $0.18-{\mu}m$ CMOS공정을 이용한 저가격의 근거리 무선통신 시스템을 구현할 수 있는 가능성을 제시한다.

• 한국컴퓨터정보학회논문지
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• 제3권2호
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• pp.77-84
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• 1998

요즈음 CMOS 기술의 발전에 의해서 연속시간 신호시스템이 매우 각광을 받고 있다. 따라서 이 논문에서는 음성신호 처리영역에서 동작하는 CMOS floating 저항을 이용한저역통과 필터를 설계하였다. 특히 이 논문에서는 포화영역에서 동작하는 all CMOS floating 저항을 설계하였으며, $\pm$1V 영역에서 $\pm$0.04%의 선형성이 얻어졌다. 주파수 응답은10MHz를 초과하였으며 능동 RC회로의 집적화에 매우 유용할것으로 생각한다. 이 방법에 의해 설계도니 저역통과필터는 SC 필터보다 그 구조가 간단하므로 IC의 형태로 만들 때 칩 면적을 많이 줄일 수 있다. 설계된 필터의 특성은 pspice에 의해 시뮬레이션 하였으며, 그 특성이 우수함이 입증되었다.

• 대한전자공학회논문지SD
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• 제40권12호
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• pp.72-79
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• 2003

본 논문에서는 CMOS 다치 논리회로를 이용한 32×32 Modified Booth 곱셈기를 제시하였다. 이 곱셈기는 Radix-4 알고리즘을 이용하였으며, 전류모드 CMOS 4차 논리회로로 구현하였다. 설계한 곱셈기는 트랜지스터 수를 기존의 전압 모드 2진 논리 곱셈기에 비해 63.2%, 이전의 다치 논리 곱셈기에 비해 37.3% 감소시켰다. 이 곱셈기는 내부 구조를 규칙적으로 배열하여 확장성을 갖도록 하였다. 설계한 회로는 3.3V의 공급전압과 단위전류 10㎂를 사용하여, 0.3㎛ CMOS 기술을 이용하여 구현하였으며 HSPICE를 사용하여 검증하였다. 시뮬레이션 결과, 설계한 곱셈기는 5.9㎱의 최대 전달지연시간과 16.9mW의 평균 전력소모 특성을 갖는다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.1239-1243
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• 2004

A novel voltage-current reference circuit for stable voltage-current applications is Proposed. Circuits for a positive and for a negative voltage-current reference are presented and are designed with commercial CMOS technology. The voltage-current reference that is stable over ambient temperature variations is an important component of most data acquisition systems. These results are verified by the HSPICE simulation $0.8{\mu}m$ parameter. As the result, the temperature dependency of output voltage and output current each is $0.57mV/^{\circ}C$, $0.11{\mu}A/^{\circ}C$ and the power dissipation is 1.8 mV on 5V supply voltage.