• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.356-359
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• 1999

A high performance 16bit multiplier for asynchronous systems has been designed using asynchronous design methodology. The 4-radix modified Booth algorithm, TSPC (true single phase clocking) registers, and modified 4-2 counters using DPTL (differential pass transistor logic) have been used in our multiplier. It is implemented in 0.65${\mu}{\textrm}{m}$ double-poly/double-metal CMOS technology by using 6616 transistors with core size of 1.4$\times$1.1$\textrm{mm}^2$. And our design results in a computation rate exceeding 60MHz at a supply voltage of 3.3V.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.1-9
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• 2009

A full adders is an important component in applications of digital signal processors and microprocessors. Thus it is imperative to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional static CMOS and pass transistor logic. The carry-out generation circuit of the proposed full adder is different from the conventional XOR-XNOR structure. The output Cout of module III is generated from input A, B and Cin directly without passing through module I as in conventional structure. Thus output Cout is faster by reducing operation step. The proposed module III uses the static CMOS logic style, which results full-swing operation and good driving capability. The proposed 1bit full adder has the advantages over the conventional static CMOS, CPL, TGA, TFA, HPSC, 14T, and TSAC logic. The delay time is improved by 4.3% comparing to the best value known. PDP(power delay product) is improved by 9.8% comparing to the best value. Simulation has been carried out using a $0.18{\mu}m$ CMOS design rule for simulation purposes. The physical design has been verified using HSPICE.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.3
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• pp.40-46
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• 2001

In this paper, a novel low power full adder circuit comprising only 10 transistors is proposed. The circuit is based on the six -transistor CMOS XOR circuit, which generates both XOR and XNOR signals and pass transistors. This adder circuit provides a good low power characteristics due to the smaller number of transistors and the elimination of short circuit current paths. Layouts have been carried out using a 0.65 ${\mu}m$ ASIC design rule for evaluation purposes. The physical design has been evaluated using HSPICE at 25MHz to 50MHz. The proposed circuit has been used to build 2bit and 8bit ripple carry adders, which are used for evaluation of power consumption, time delay and rise and fall time. The proposed circuit shows substantially improved power consumption characteristics, about 70% lower than transmission gate full adder (TFA), and 60% lower than a design using 14 transistors (TR14). Delay and signal rise and fall time are also far shorter than other conventional designs such as TFA and TR14.

• ETRI Journal
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• v.39 no.3
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• pp.373-382
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• 2017

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of $433.80{\mu}V/mA$ and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of $1{\mu}s$. The total current consumption is $17.88{\mu}V/mA$ (for a 0.9 V supply voltage).

• Journal of IKEEE
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• v.19 no.4
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• pp.506-513
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• 2015

In this paper, an output-capacitorless, low-dropout (LDO) regulator is designed, which consumes $4.5{\mu}A$ quiescent current. Proposed LDO regulator is realized using two amplifier for good load regulation and fast response time, which provide high gain, high bandwidth, and high slew rate. In addition, a one-shot current boosting circuit is added for current control to charge and discharge the parasitic capacitance at the pass transistor gate. As a result, response time is improved during load-current transition. The designed circuit is implemented through a $0.11-{\mu}m$ CMOS process. We experimentally verify output voltage fluctuation of 260mV and recovery time of $0.8{\mu}s$ at maximum load current 200mA.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.311-323
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• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.