• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.270-273
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• 2000

We have fabricated and analyzed photodiodes for optical link with Si pin structures. As the results of experiment, the web patterned photodiode(type C) with $p^{+}$-guard ring showed low junction capacitance of 6~7 pF at $V_{R}$=-5V and high separation ability for optical signal(dark current : $\leq$ 5 nA, optical signal current : $\geq$ 340 nA) due to the small effective $p^{+}$-n junction area and the expanded electric field region. The fabricated Si pin photodiode can be applicable for detecting an optical signal with the wavelength of about 660~670 nm. It can also be integrated with the twin well CMOS structure to develope an one chip based optical receiver IC. IC.C.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.210-216
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• 2004

In this paper, we propose a noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection with noise power calibration for low power applications. The proposed UWB system achieves good bit error rate performance which is favorably comparable to that of the system using the ideal adaptive threshold, while maintaining simple receiver structure, In addition, low power Analog Front-End (AFE) blocks for the proposed noncoherent UWB transceiver are proposed and verified using CMOS technology. Simulation results on the pulse generator, delay time generator and 1-bit Analog-to-Digital (AID) converter show feasibility of the proposed UWB AFE system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.839-842
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• 1998

The wide spread of multimedia system demands a large viewin gdesply device which can inform a message to many peoples in open area. This paper is about the design, simulating and testing of a large viewing LED pannel control ASIC(application specific integrated circuit). This LED pannel control ASIC runs on 16 bit microprocessor MC68EC000 and has following functions:16 line interlaced LED pannel controller, memory controller, 16 channel priority inerrupt controller, 2 channel direct memory access controller, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16byte FIFO, IBM PC/AT compatible keyboard interface, battery backuped real time clock, ISA bus controller, battery backuped 256 byte SRAM and watech dog timer. The 0.6micron CMOS sea of gate is used to design the ASIC in amount of about 39,000 gates.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.887-890
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• 2003

High Speed data transmission over a long length of cable is limited due to the limited bandwidth of a cable which introduces ISI(Inter Symbol Interference). In order to compensate for the loss and phase dispersion in the cable, a pulse shaping in a transmitter and a line equalizer in receiver can be used. This paper presents a low-power and small-ana analog adaptive pulse shaping circuit and line equalizer, The design was fabricated in a 0.25${\mu}{\textrm}{m}$ mixed-signal CMOS process. The proposed pulse shaping circuit and equalizer operate at 400Mb/s on 50m STP(Shielded Twisted Pair) cable. It consumes 28.5${\mu}{\textrm}{m}$ with a 2.5-V power supply and occupies only 0.098 $\textrm{mm}^2$.

• IEIE Transactions on Smart Processing and Computing
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• 제3권6호
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• pp.410-415
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• 2014

This paper presents a new rectifier with a bootstrapping technique to reduce the effective drop voltage. An all-digital delay locked loop (ADDLL) circuit was also applied to prevent the reverse leakage current. The proposed rectifier uses NMOS diode connected instead of PMOS to reduce the design size and improve the frequency respond. All the sub-circuits of ADDLL were designed with low power consumption to reduce the total power of the rectifier. The rectifier was implemented in CMOS $0.35{\mu}m$ technology. The peak power conversion efficiency was 76 % at an input frequency of 6.78MHz and a power level of 5W.

• Journal of electromagnetic engineering and science
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• 제14권4호
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권4호
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• pp.176-181
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• 2001

As the data rate between chip-to-chip gets high, the skin effect and load of pins deteriorate noise margin. With these, noise disturbances on the bus channel make it difficult for receiver circuits to read the data signal. This paper has proposed a new pre-emphasis driver circuit which achieves wide noise margin by enlarging the signal voltage range during data transition. When data is transferred from a memory chip to a controller, the output boltage of the driver circuit reaches the final values through the intermediate voltage level. The proposed driver supplies more currents applicable to a packet-based memory system, because it needs no additional control signal and realizes very small area. The circuit has been designed in a 0.18 ${\mu}m$ CMOS process, and HSPICE simulation results have shown that the data rate of 1.32 Gbps be achieved. Due to its result, the proposed driver can achieved higher speed than conventional driver by 10%.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 D
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• pp.3127-3129
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• 2000

본 논문에서는 광 다이오드에서 들어오는 신호로부터 원하는 대역의 신호를 얻기 위한 적외선 수신 IC에 적합한 대역통과필터를 설계하였다 설계한 대역통과필터는 2차 Biquad gm-C 필터의 구조를 이용하여 중심주파수가 38kHz. Quality factor가 10인 필터를 구현하였다. 구현된 대역통과필터는 필터부분과 중심주파수를 보정해 주는 frequency tuning 부분으로 구성되어 있다. 낮은 transconductance와 높은 선형성을 요구하는 transconductor의 설계를 위해 Gilbert 곱셈기 특성을 이용하여 구현하였고 AMS사의 0.8${\mu}m$ BiCMOS model을 사용하여 +5V로 동작되도록 설계 하였다

• ETRI Journal
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• 제30권4호
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• pp.612-614
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• 2008

A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared pre-amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.

• 한국정보처리학회논문지
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• 제6권5호
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• pp.1351-1361
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• 1999

The wide spread of multimedia system demands a large area viewing display device which can inform a message to many people in open area. This paper is about the design of a large area viewing LED panel control system. The control system runs on 16 bit microprocessor MC68EC000 and has following functions: 16 line clock and time, 2 channel priority interrupt, 2 channel direct memory access, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16 byte FIFO, IBM PC/AT compatible keyboard interface, ISA bus, battery backuped real time clock, battery backuped 256 byte SRAM and watch dog timer. The core circuits are implemented to ASIC, considering lower cost, higher reliability, higher performance, smaller dimension, and lower power consumption. This is verified by simulation and fabricated in 0.6 um CMOS SOG processes. The total gate count is 39,083 and the clock frequency is 48 MGz. The fabricated ASIC is mounted on test board.