• The Journal of the Korea Contents Association
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• v.13 no.10
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• pp.54-61
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• 2013

This paper presents a simplified hardware based edge detection circuit which is based on an analog correlator combining with the neighbor pixels in CMOS image sensor. A pixel element of the edge detector consists of an active pixel sensor and an analog correlator circuit which connects two neighbor pixels. The edge detector shares a comparator on each column that the comparator decides an edge of the target pixel with an adjustable reference voltage. The circuit detects image edge from CIS directly that reduces area and power consumption 4 times and 20%, respectively, compared with the previous works. And also it has advantage to regulate sensitivity of the edge detection because the threshold value is able to control externally. The fabricated chip has 34% of fill factor and 0.9 ${\mu}W$ of power per a pixel under 0.18 ${\mu}m$ CMOS technology.

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.349-354
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• 2010

Moving pixel displacement detection algorithm using correlation functions for making panorama image on the continuous images is presented in this paper. The input images get from a CMOS image sensor (CIS). The camera is maintained by constant brightness and uniform sensing area in test input pattern. For simple navigation and capture image has to 70% overlapped region. A correlation rate in two image data is evaluated by using reference image with first captures, and compare image with next captures. The displacement of the two images are expressed to second order function of x, y and solved with finding the coefficient in second order function. That results in the change in the peak correlation displacement from the reference to the compare image, is moving to pixel length. The navigating error is reduced by varying the path because the error is shown in the difference of the positioning vector between the true pixel position and the navigated pixel position. The algorithm performance is evaluated to be different from the error vector to vary the navigating path grid.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.687-688
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• 2006

This paper presents implementation of the lifting based DWT processor interface which the process of JPEG2000. The proposed architecture uses Excalibur device produced Altera. This study describes CIS(CMOS Image Sensor), DMA(Direct Memory Access) and DWT control logic

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.1
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• pp.191-196
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• 2021

In this paper, we implemented an image sensor module possible of detecting color temperature in an indoor environment. The color temperature information in the video information acquired by the image sensor was matched with a color difference illuminometer to produce an LUT. An algorithm was developed so that color temperature information according to the received RGB values can be automatically calculated. As a result of measuring the color temperature with an image sensor indoors, an accurate result of less than 5.91% was obtained compared to the reference value. It was confirmed that the uniformity of 23.5% or more was excellent compared to the color temperature measurement result using a color sensor.

• Journal of Sensor Science and Technology
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• v.15 no.2
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• pp.112-119
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• 2006

Resolution of an image sensor is very significant parameter to improve. It is hard to improve the resolution of the CMOS vision chip for edge detection based on a biological retina using a resistive network because the vision chip contains additional circuits such as a resistive network and some processing circuits comparing with general image sensors such as CMOS image sensor (CIS). In this paper, we proved the problem of low resolution by separating photo-sensing and signal processing circuits. This type of vision chips occurs a problem of low operation speed because the signal processing circuits should be commonly used in a row of the photo-sensors. The low speed problem of operation was proved by using a reset decoder. A vision chip for edge detection with $128{\times}128$ pixel array has been designed and fabricated by using $0.35{\mu}m$ 2-poly 4-metal CMOS technology. The fabricated chip was integrated with optical lens as a camera system and investigated with real image. By using this chip, we could achieved sufficient edge images for real application.

• Journal of Radiation Industry
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• v.9 no.1
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• pp.1-7
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• 2015

The trend of x-ray image sensor has been evolved from an amorphous silicon sensor to a crystal silicon sensor. A crystal silicon X-ray sensor, meaning a X-ray CIS (CMOS image sensor), is consisted of three transistors (Trs), i.e., a Reset Transistor, a Source Follower and a Select Transistor, and a photodiode. They are highly sensitive to radiation exposure. As the frequency of exposure to radiation increases, the quality of the imaging device dramatically decreases. The most well known effects of a X-ray CIS due to the radiation damage are increments in the reset voltage and dark currents. In this study, a pixel array of a X-ray CIS was made of $20{\times}20pixels$ and this pixel array was exposed to a high radiation dose. The radiation source was Co-60 and the total radiation dose was increased from 1 to 9 kGy with a step of 1 kGy. We irradiated the small pixel array to get the increments data of the reset voltage and the dark currents. Also, we simulated the radiation effects of the pixel by MCNP (Monte Carlo N-Particle) simulation. From the comparison of actual data and simulation data, the most affected location could be determined and the cause of the increments of the reset voltage and dark current could be found.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.87-95
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• 2014

This paper describes a dual channel receiver design for CIS interfaces. Each channel includes CTLE(Continuous Time Linear Equalizer), sampler, deserializer and clocking circuit. The clocking circuit is composed of PLL, PI and CDR. Fast lock acquisition time, short latency and better jitter tolerance are achieved by adding OSPD(Over Sampling Phase Detector) and FSM(Finite State Machine) to PI-based CDR. The CTLE removes ISI caused by channel with -6 dB attenuation and the lock acquisition time of the CDR is below 1 baud period in frequency offset under 8000ppm. The voltage margin is 368 mV and the timing margin is 0.93 UI in eye diagram using 65 nm CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2365-2373
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• 2011

This paper propose the hardware IP of real-time face detection system for mobile devices and digital cameras required for high speed, smaller size and lower power. The proposed face detection system is robust against illumination changes, face size, and various face angles as the main cause of the face detection performance. Input image is transformed to LBP(Local Binary Pattern) image to obtain face characteristics robust against illumination changes, and detected the face using face feature data that was adopted to learn and generate in the various face angles using the Adaboost algorithm. The proposed face detection system can be detected maximum 36 faces at the input image size of QVGA($320{\times}240$), and designed by Verilog-HDL. Also, it was verified hardware implementation by using Virtex5 XC5VLX330 FPGA board and HD CMOS image sensor(CIS) for FPGA verification.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.1
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• pp.27-31
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• 2009

In this paper, the polymer adhesive bonding technology using wafer-level technology was investigated and warpage results were analyzed. Si and glass wafer was bonded after adhesive polymer layer and dam pattern for uniform state was patterned on glass wafer. In this study, warpage result decreased as the low of bonding temperature of Si wafer, bonding pressure and height of adhesive bonding layer. The availability of adhesive polymer bonding was confirmed by TC, HTC, Humidity soak test after dicing. The result is that defect has not found without reference to warpage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.503-506
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• 2015

In accordance with IoT(Internet of Things) commercialization, the need to design SoC-based hardware platform with wireless communication is increasing. This paper therefor proposes an SoC platform architecture with Smart Frame System inter-communicating between devices. Wireless communication functions and high-performance real-time image processing hardware structure was applied to existing digital photo frame. We developed a smart phone application to control the smart frame through Bluetooth communication. The SoC platform hardware consists of CIS controller, Memory controller, ISP(Image Signal Processing) module for image scaling, Bluetooth Interface for inter-communicating between devices, VGA/TFT-LCD controller for displaying video. The Smart Frame System to support the IoT services was implemented and verified using HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA. The operating frequency is 54MHz.