• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.14 no.6
• /
• pp.479-486
• /
• 2021

In this paper, an ultra small phase locked loop (PLL) with a single capacitor loop filter has been proposed by adding a signal sensing circuit (SSC). In order to extremely reduce the size of the PLL, the passive element loop filter, which occupies the largest area, is designed with a very small single capacitor (2pF). The proposed PLL is designed to operate stably by the output of the internal negative feedback loop including the SSC acting as a negative feedback to the output of the single capacitor loop filter of the external negative feedback loop. The SSC that detects the PLL output signal change reduces the excess phase shift of the PLL output frequency by adjusting the capacitance charge of the loop filter. Although the proposed structure has a capacitor that is 1/78 smaller than that of the existing structure, the jitter size differs by about 10%. The PLL is designed using a 1.8V 180nm CMOS process and the Spice simulation results show that it works stably.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
• /
• v.7 no.10
• /
• pp.895-903
• /
• 2017

Quantum Cellular Automata(QCA) is one of the proposed techniques as an alternative solution to the fundamental limitations of CMOS. QCA has recently been extensively studied along with experimental results, and is attracting attention as a nano-scale size and low power consumption. Although the XOR gates proposed in the previous paper can be designed using the minimum area and the number of cells, there is a disadvantage that the number of added cells is increased due to the stability and the accuracy of the result. In this paper, we propose a gate that supplement for the drawbacks of existing XOR gates. The XOR gate of this paper reduces the number of cells by arranging AND gate and OR gate with square structure and propose a half-adder by adding two cells that serve as simple inverters using the proposed XOR gate. Also This paper use QCADesginer for input and result accuracy. Therefore, the proposed half-adder is composed of fewer cells and total area compared to the conventional half-adder, which is effective when used in a large circuit or when a half - adder is needed in a small area.

• International journal of advanced smart convergence
• /
• v.11 no.4
• /
• pp.96-103
• /
• 2022

This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm². In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.

• Journal of Sensor Science and Technology
• /
• v.33 no.2
• /
• pp.112-116
• /
• 2024

Gas-sensor technology for volatile organic compounds (VOC) biomarker detection offers significant advantages for noninvasive diagnostics, including rapid response time and low operational costs, exhibiting promising potential for disease diagnosis. Colorimetric gas sensors, which enable intuitive analysis of gas concentrations through changes in color, present additional benefits for the development of personal diagnostic kits. However, the traditional method of visually monitoring these sensors can limit quantitative analysis and consistency in detection threshold evaluation, potentially affecting diagnostic accuracy. To address this, we developed a machine vision platform based on metal-organic framework (MOF) for colorimetric gas sensor arrays, designed to accurately detect disease-related VOC biomarkers. This platform integrates a CMOS camera module, gas chamber, and colorimetric MOF sensor jig to quantitatively assess color changes. A specialized machine vision algorithm accurately identifies the color-change Region of Interest (ROI) from the captured images and monitors the color trends. Performance evaluation was conducted through experiments using a platform with four types of low-concentration standard gases. A limit-of-detection (LoD) at 100 ppb level was observed. This approach significantly enhances the potential for non-invasive and accurate disease diagnosis by detecting low-concentration VOC biomarkers and offers a novel diagnostic tool.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.9
• /
• pp.58-67
• /
• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.

• Progress in Medical Physics
• /
• v.19 no.2
• /
• pp.102-112
• /
• 2008

We developed a high-resolution micro-CT system based on rotational gantry and flat-panel detector for live mouse imaging. This system is composed primarily of an x-ray source with micro-focal spot size, a CMOS (complementary metal oxide semiconductor) flat panel detector coupled with Csl (TI) (thallium-doped cesium iodide) scintillator, a linearly moving couch, a rotational gantry coupled with positioning encoder, and a parallel processing system for image data. This system was designed to be of the gantry-rotation type which has several advantages in obtaining CT images of live mice, namely, the relative ease of minimizing the motion artifact of the mice and the capability of administering respiratory anesthesia during scanning. We evaluated the spatial resolution, image contrast, and uniformity of the CT system using CT phantoms. As the results, the spatial resolution of the system was approximately the 11.3 cycles/mm at 10% of the MTF curve, and the radiation dose to the mice was 81.5 mGy. The minimal resolving contrast was found to be less than 46 CT numbers on low-contrast phantom imaging test. We found that the image non-uniformity was approximately 70 CT numbers at a voxel size of ${\sim}55{\times}55{\times}X100\;{\mu}^3$. We present the image test results of the skull and lung, and body of the live mice.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.9
• /
• pp.63-73
• /
• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.5
• /
• pp.87-97
• /
• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• Korean Journal of Remote Sensing
• /
• v.37 no.6_3
• /
• pp.1985-1999
• /
• 2021

The purpose of this study is to apply urban heat island reduction techniques(green roof, cool roof, and cool pavements using heat insulation paint or blocks) recommended by the Environmental Protection Agency (EPA) to our study area and determine their actual effects through a comparative analysis between land cover objects. To this end, the area of Mugye-ri, Jangyu-myeon, Gimhae, Gyeongsangnam-do was selected as a study area, and measurements were taken using a drone DJI Matrice 300 RTK, which was equipped with a thermal infrared sensor FLIR Vue Pro R and a visible spectrum sensor H20T 1/2.3" CMOS, 12 MP. A total of nine heat maps, land cover objects (711) as a control group, and heat island reduction technique-applied land covering objects (180) were extracted every 1 hour and 30 minutes from 7:15 am to 7:15 pm on July 27. After calculating the effect values for each of the 180 objects extracted, the effects of each technique were integrated. Through the analysis based on daytime hours, the effect of reducing heat islands was found to be 4.71℃ for cool roof; 3.40℃ for green roof; and 0.43℃ and -0.85℃ for cool pavements using heat insulation paint and blocks, respectively. Comparing the effect by time period, it was found that the heat island reduction effect of the techniques was highest at 13:00, which is near the culmination hour, on the imaging date. Between 13:00 and 14:30, the efficiency of temperature reduction changed, with -8.19℃ for cool roof, -5.56℃ for green roof, and -1.78℃ and -1.57℃ for cool pavements using heat insulation paint and blocks, respectively. This study was a case study that verified the effects of urban heat island reduction techniques through the use of high-resolution images taken with drones. In the future, it is considered that it will be possible to present case studies that directly utilize micro-satellites with high-precision spatial resolution.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.9C
• /
• pp.861-870
• /
• 2002

In this paper, with targeting on the drawback of RSA of operation speed, a new 1024-bit RSA cryptosystem has been proposed and implemented in hardware to increase the operational speed and perform the variable-length encryption. The proposed cryptosystem mainly consists of the modular exponentiation part and the modular multiplication part. For the modular exponentiation, the RL-binary method, which performs squaring and modular multiplying in parallel, was improved, and then applied. And 4-stage CSA structure and radix-4 booth algorithm were applied to enhance the variable-length operation and reduce the number of partial product in modular multiplication arithmetic. The proposed RSA cryptosystem which can calculate at most 1024 bits at a tittle was mapped into the integrated circuit using the Hynix Phantom Cell Library for Hynix 0.35㎛ 2-Poly 4-Metal CMOS process. Also, the result of software implementation, which had been programmed prior to the hardware research, has been used to verify the operation of the hardware system. The size of the result from the hardware implementation was about 190k gate count and the operational clock frequency was 150㎒. By considering a variable-length of modulus number, the baud rate of the proposed scheme is one and half times faster than the previous works. Therefore, the proposed high speed variable-length RSA cryptosystem should be able to be used in various information security system which requires high speed operation.