• 재활복지
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• v.22 no.3
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• pp.225-257
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• 2018

The purpose of this study is to find the application point of hearing augmentation technology development through examining the risk context experience of people with hearing impairment and the use of assistive device used as an alternative technology. Data of 355 people with hearing impairment with official disability grading was analyzed. The results of this study are first, research participants had no experience of recognizing any sound or vibration in situations highest in the order of means of transportation, material, and nature. Especially the ratio of being unable to recognize the sound and vibration of means of transportation was high, which implies the high possibility of people with hearing impairment experiencing risk. Secondly, the risk context that people with hearing impairment will most likely to experience are highest in the order of traffic accident, pedestrian accident, and daily life at home. Thirdly, the recognition of 2G phone/smart phone, vibrating digital alarm clock, light bar, vibrating wrist watch as assistive device for risk context awareness and notification was high and the satisfaction level of 2G phone/smart phone was the highest. Fourthly, the research participants had high recognition of assistive device for communication in the order of hearing aid, smart phone, videophone, cochlear implant and 2G phone and it was found that the satisfaction level and communication improvement level was the highest using the smart phone. Lastly, for the development of hearing augmentation technology the research participants recognized the importance of portable/wear convenience, price, and motion accuracy and for notification delivery means they preferred the method of using sight(text and light). Based on the results of this study policy and practical plans for hearing augmentation technology development for people with hearing impairment in risk context are proposed.

• Journal of IKEEE
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• v.22 no.4
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• pp.1025-1030
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• 2018

The proposed modulator is designed by utilizing a conventional structure employing time division technique to realize the 4th order delta-sigma modulator using one op-amp. In order to reduce the influence of KT/C noise, the capacitance in the first and second integrators reused was chosen to be 20pF and capacitance of third and fourth integrators was designed to be 1pF. The stage variable technique in the low power reconfigurable op-amp was used to solve the stability issue due to different capacitance loads for the reduction of KT/C noise. This technique enabled the proposed modulator to reduce the power consumption of 15% with respect to the conventional one. The proposed modulator was fabricated with 0.18um CMOS N-well 1 poly 6 metal process and consumes 305uW at supply voltage of 1.8V. The measurement results demonstrated that SNDR, ENOB, DR, FoM(Walden), and FoM(Schreier) were 66.3 dB, 10.6 bits, 83 dB, 98 pJ/step, and 142.8 dB at the sampling frequency of 256kHz, oversampling ratio of 128, clock frequency of 1.024 MHz, and input frequency of 250 Hz, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.755-758
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• 2014

In this paper, we propose effective Deblocking Filter hardware architecture for High Efficiency Video Coding encoder. we propose Deblocking Filter hardware architecture with less processing time, filter ordering for low area design, effective memory architecture and four-pipeline for a high performance HEVC(High Efficiency Video Coding) encoder. Proposed filter ordering can be used to reduce delay according to preprocessing. It can be used for realtime single-port SRAM read and write. it can be used in parallel processing by using two filters. Using 10 memory is effective for solving the hazard caused by a single-port SRAM. Also the proposed filter can be used in low-voltage design by using clock gating architecture in 4-pipeline. The proposed Deblocking Filter encoder architecture is designed by Verilog HDL, and implemented by 100k logic gates in TSMC $0.18{\mu}m$ process. At 150MHz, the proposed Deblocking Filter encoder can support 4K Ultra HD video encoding at 30fps, and can be operated at a maximum speed of 200MHz.

• Journal of Conservation Science
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• v.37 no.2
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• pp.101-119
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• 2021

Korea's National Treasure No. 229, the Jagyeongnu (clepsydra) of Changgyeonggung Palace, is a scientific and cultural property representing the pinnacle of science and technology in the Joseon Dynasty. Currently, only the large, mid-sie, and small Pasuhos (bronze jars) remain. During a nearly two-year conservation project by the Cultural Heritage Conservation Science Center (CHCSC) that began in 2018, conservators identified the contaminants on the surface of the water clock's components. It turned out that the contaminants had been caused by the exposure of squalane and silicone oil, used in an earlier preservation treatment, to the elements. The CHCSC conducted experiments to determine the most effective method to remove the contaminants. First, the conservators tried using an organic solvent, a poultice, and the application of toluene and bentonite, which yielded excellent reactivity and significant color difference changes (𝚫E). However, the reactivity was insufficiently effective to warrant the health hazards to the conservators and the environment (toluene is toxic). Although organic solvents required considerably more effort, time, and human resources, the conservators confirmed that their use achieved a true color difference variation (𝚫E) that was within the same range as the toxic hydrocarbon. Thus, they confirmed that using an organic surfactant was the best method for removing the contaminants.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.81-93
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• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.2
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• pp.201-211
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• 2012

This paper addresses a Full Disk Encryption hardware processor for SATA HDD in a single FPGA design, and shows its experimental result using an FPGA board. The proposed processor mainly consists of two blocks: the first block processes XTS-AES block cipher which is the IEEE P1619 standard of storage media encryption and the second block executes the interface between SATA Host (PC) and Device (HDD). To minimize the performance degradation, we designed the XTS-AES block with the 4-stage pipelined structure which can process a 128-bit block per 4 clock cycles and has 4.8Gbps (max) performance. Also, we implemented the proposed design with Xilinx ML507 FPGA board and our experiment showed 140MB/sec read/write speed in Windows XP 32-bit and a SATA II HDD. This performance is almost equivalent with the speed of the direct SATA connection without FDE devices, hence our proposed processor is very suitable for SATA HDD Full Disk Encryption environments.

• Journal of Ginseng Research
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• v.45 no.1
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• pp.183-190
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• 2021

Background: The circadian rhythm is the internal clock that controls sleep-wake cycles, metabolism, cognition, and several processes in the body, and its disruption has been associated with aging. The differentiated embryo chondrocyte (Dec) gene is related to circadian rhythm. To our knowledge, there are no reports of the relationship between dec gene expression and KRG effect. Therefore, we treated Dec gene knockout (KO) aging mice with KRG to study anti-aging related effects and possible mechanisms. Methods: We evaluated KRG and expression of Dec genes in an ototoxicity model. Dec genes expression in livers of aging mice was further analyzed. Then, we assessed the effects of DEC KO on hearing function in mice by ABR. Finally, we performed DNA microarray to identify KRG-related gene expression changes in mouse liver and assessed the results using KEGG analysis. Results: KRG decreased the expression of Dec genes in ototoxicity model, which may contribute to its anti-aging efficacy. Moreover, KRG suppressed Dec genes expression in liver of wild type indicating inhibition of senescence. ABR test indicated that KRG improved auditory function in aging mouse, demonstrating KRG efficacy on aging related diseases. Conclusion: Finally, in KEGG analysis of 238 genes that were activated and 158 that were inhibited by KRG in DEC KO mice, activated genes were involved in proliferation signaling, mineral absorption, and PPAR signaling whereas the inhibited genes were involved in arachidonic acid metabolism and peroxisomes. Our data indicate that inhibition of senescence-related Dec genes may explain the anti-aging efficacy of KRG.

• Journal of IKEEE
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• v.25 no.4
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• pp.625-633
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• 2021

This paper describes a scalable architecture for flexible hardware implementation of Montgomery modular multiplication. Our scalable modular multiplier architecture, which is based on a one-dimensional array of processing elements (PEs), performs word parallel operation and allows us to adjust computational performance and hardware complexity depending on the number of PEs used, N_PE. Based on the proposed architecture, we designed a scalable Montgomery modular multiplier (sMM) core supporting eight field sizes defined in SEC2. Synthesized with 180-nm CMOS cell library, our sMM core was implemented with 38,317 gate equivalents (GEs) and 139,390 GEs for N_PE=1 and N_PE=8, respectively. When operating with a 100 MHz clock, it was evaluated that 256-bit modular multiplications of 0.57 million times/sec for N_PE=1 and 3.5 million times/sec for N_PE=8 can be computed. Our sMM core has the advantage of enabling an optimized implementation by determining the number of PEs to be used in consideration of computational performance and hardware resources required in application fields, and it can be used as an IP (intellectual property) in scalable hardware design of elliptic curve cryptography (ECC).

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.10
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• pp.373-380
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• 2022

This paper presents a deep learning based group synchronization that supports networked immersive interactions between remote users. The goal of group synchronization is to enable all participants to synchronously interact with others for increasing user presence Most previous methods focus on NTP-based clock synchronization to enhance time accuracy. Moving average filters are used to control media playout time on the synchronization server. As an example, the exponentially weighted moving average(EWMA) would be able to track and estimate accurate playout time if the changes in input data are not significant. However it needs more time to be stable for any given change over time due to codec and system loads or fluctuations in network status. To tackle this problem, this work proposes the Deep Group Synchronization(DeepGroupSync), a group synchronization based on deep learning that models important features from the data. This model consists of two Gated Recurrent Unit(GRU) layers and one fully-connected layer, which predicts an optimal playout time by utilizing the sequential playout delays. The experiments are conducted with an existing method that uses the EWMA and the proposed method that uses the DeepGroupSync. The results show that the proposed method are more robust against unpredictable or rapid network condition changes than the existing method.