• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.136-139
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• 2003

A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of signal amplifiers, a nonlinear circuit with diodes, and a bandpass filter Before implementing the 40 Gb/s clock recovery circuit, a 10 Gb/s clock recovery circuit has been successfully implemented and tested. With the 40 Gb/s clock recovery circuit, when a 40 Gb/s NRZ signal of -10 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -20 dBm output power after passing through the nonlinear circuit. The output signal from the nonlinear circuit passes through a narrow-band filter, and then amplified. The implemented clock recovery circuit is planned to be used for the input of a phase locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.81-85
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• 1999

DWMT VDSL system needs A/D converter clock, bit clock, symbol clock, frame clock, etc. DMT ADSL system utilizes a correlation method which makes use of cyclic prefix or preamble pattern for clock recovery. But the correlation method is difficult to apply to the DWMT system because modulated symbols are overlapped in the time domain. This paper proposes a novel clock recovery method which can be used for the DWMT system due to its inherent independence of the modulation method. This new method is verified by SPICE simulations.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.865-868
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• 2005

This paper presents a Clock-gating technique that reduces power dissipation of the sequential circuits in the system. The Master Clock of a Clock-gating technique is formed by a quaternary variable. It uses the covering relationship between the triggering transition of the clock and the active cycles of various flip-flops to generate a slave clock for each flip-flop in the circuit. At current RTL designs flip-flop is acted by Master clock's triggering but the Slave Clock of Clock-gating technique doesn't occur trigger when external input conditions have not matched with a condition of logic table. We have applied our clocking technique to UART controller of 8bit microprocess

• Animal cells and systems
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• 제16권1호
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• pp.1-10
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• 2012

Most living organisms synchronize their physiological and behavioral activities with the daily changes in the environment using intrinsic time-keeping systems called circadian clocks. In mammals, the key molecular features of the internal clock are transcription- and translational-based negative feedback loops, in which clock-specific transcription factors activate the periodic expression of their own repressors, thereby generating the circadian rhythms. CLOCK and BMAL1, the basic helix-loop-helix (bHLH)/PAS transcription factors, constitute the positive limb of the molecular clock oscillator. Recent investigations have shown that various levels of posttranslational regulation work in concert with CLOCK/BMAL1 in mediating circadian and cellular stimuli to control and reset the circadian rhythmicity. Here we review how the CLOCK and BMAL1 activities are regulated by intracellular distribution, posttranslational modification, and the recruitment of various epigenetic regulators in response to circadian and cellular signaling pathways.

• Journal of Electrical Engineering and Technology
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• 제7권3호
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• pp.429-435
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• 2012

In this study, a real-time architecture for the detection of clock jumps in the GPS clock behavior is proposed. GPS satellite atomic clocks have characteristics of a second order polynomial in the long term showing sudden jumps occasionally. As satellite clock anomalies influence on GPS measurements which could deliver wrong position information to users as a result, it is required to develop a real time technique for the detection of the clock anomalies especially on the real-time GPS applications such as aviation. The proposed strategy is based on Teager Energy operator, which can be immediately detect any changes in the satellite clock bias estimated from GPS carrier phase measurements. The verification results under numerous cases in the presence of clock jumps are demonstrated.

• 정보처리학회논문지C
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• 제16C권5호
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• pp.637-644
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• 2009

NG-SDH망에서 측정된 클럭잡음을 이용한 동기클럭 성능분석 연구가 필요하다. 따라서 본 논문은 NG-SDH망에서 측정된 클럭잡음을 이용하여 다양한 클럭상태에 따른 동기클럭 성능을 분석하고 최대 망노드수를 도출하기 위한 연구를 수행하였다. 또한 측정된 클럭잡음을 이용하여 적합한 클럭잡음모델을 생성하였고, 다양한 클럭상태에 따른 시뮬레이션을 수행하였다. 시뮬레이션 결과를 통해 볼 때 정상상태에서 최대노드수는 80개 노드 이상 이였고, 단기위상변위(SPT)상태에서는 37개 이하였고, 장기위상변위(LPT)상태에서는 50개 이상으로 나타났다. 따라서 3가지 클럭상태에서 ITU-T 규격을 만족할 수 있는 최대 노드수는 37개 이하 임을 알았다. 또한 DOTS 이전의 NE망에서 SPT이나 LPT상태가 발생하면 정상상태의 안정된 다른 동기원 소스로 절체해야 함을 알았다.

• Animal cells and systems
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• 제9권3호
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• pp.153-160
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• 2005

Most living organisms exhibit the circadian rhythm in their physiology and behavior. Recent identification of several clock genes in mammals has led to the molecular understanding of how these components generate and maintain the circadian rhythm. Many reports have implicated the photic induction of either mPer1 or mPer2 in the hypothalamic region called the suprachiasmatic nucleus (SCN) to phase shift the brain clock. It is now established that peripheral tissues other than the brain also express these clock genes and that the clock machinery in these tissues work in a similar way to the SCN clock. To determine the role of the two canonical clock genes, mPer1 and mPer2, in the peripheral clock shift, stable HEK293EcR cell lines that can be induced and stably express these proteins were prepared. By regulating the expression of these proteins, it could be shown that induction of the clock genes, either mPer1 or mPer2 alone is not sufficient to cause clock phase shifting in these cells. Our real-time PCR analysis on these cells indicates that the induction of mPER proteins dampens the expression of the clock-specific transcription factor mBmal1. Altogether, our present data suggest that mPer1 and mPer2 may not function in clock shift or take part in differential roles on the peripheral circadian clock.

• 한국전자파학회논문지
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• 제15권2호
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• pp.134-139
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• 2004

40 Gb/s 광 수신기용 클락 복원회로를 설계 및 제작하였다. 클락 복원회로는 전치 증폭기, 다이오드를 이용한 비선형 회로, 대역통과 필터, 클락 증폭기로 구성되어 있다. 40 Gb/s 클락 복원회로를 제작하기에 앞서 10 Gb/s 클락 복원회로를 제작, 측정하였다. 40 Gb/s 클락 복원회로에 -10 dBm의 40 Gb/s NRZ 신호를 입력하였을 때, 비선형 회로를 통과한 후에 40 GHz의 클락이 출력 전력 -20 dBm으로 복원되었다. 비선형 회로를 통과하여 복원된 클락은 협대역 필터를 통과하고, 증폭되게 된다. 제작된 클락 복원회로는 클락의 지터를 감소시키고, 더욱 안정화 시키기 위하여 위상 동기 회로의 입력으로 사용되게 된다.

• 제어로봇시스템학회논문지
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• 제19권2호
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• pp.125-130
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• 2013

Compared to OWR (One-Way Ranging) method that requires precise network time synchronization, TWR (Two-Way Ranging) method has advantages in building an indoor WPAN (Wireless Personal Area Network) location system with lower cost. However, clock offsets of nodes in WPAN system should be eliminated or compensated to improve location accuracy of the TWR method. Because conventional clock offset elimination methods requires multiple TWR transactions to reduce clock offset, they produce network traffic burden instead. This paper presents a clock offset estimation method that can reduce clock offset error with a single TWR transaction. After relative clock offsets of sensor nodes are estimated, clock offsets of mobile tags are estimated using a single TWR communication. Simulation results show that location accuracy of the proposed method is almost similar to the conventional clock offset elimination method, while its network traffic is about a half of the conventional method.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2005년도 종합학술발표회 논문집 Vol.15 No.1
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• pp.191-196
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• 2005

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver has been designed and implemented. It consists of a clock recovery circuit, a RF mixer and frequency discriminator for phase/frequency detection, a DR-VCO, a phase shifter, and a hold circuit. The recovered 40 GHz clock is synchronized with a stable 10 GHz DR-VCO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module has shown to significantly improve the performance of the conventional open-loop type clock recovery module with DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When input signal is dropped, the 40 GHz clock is generated continuously by hold circuit. The implemented clock recovery module can be used as a low-cost and high-performance receiver module for 40 Gb/s commercial optical network.