• Title/Summary/Keyword: CLB

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Prevalence and Cytotoxic Effects of Some Colibactin and cnf Genes among Escherichia coli Isolated from Urinary Tract Infections

  • Alhadidi, Hiba A.S.;Al-Qaysi, Safaa A. S.;Al-Halbosiy, Mohammad M. F.
    • Microbiology and Biotechnology Letters
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    • v.50 no.2
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    • pp.283-292
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    • 2022
  • Colibactins (clb) and Cytotoxic Necrotizing Factors (cnf) are virulence factors that impact cell cycle through cellular differentiation, proliferation, and apoptosis. Urinary tract infections (UTIs) are the most common among type of infection among outpatients, with a lifetime incidence of about 60-65% in adult females. Here, we sought to isolate uropathogenic Escherichia coli (UPCE) from urine specimens and investigates the prevalence of clb A, B and cnf 1, 2 genes among these isolates. A total of 110 E. coli isolates were collected from patients with UTIs. All the isolates were examined for their hemolytic activity and only 46 isolates showed a halo zone of hemolysis on blood agar. The collected UPEC isolates were screened for the existence of clb A, B and cnf genes. The results revealed that out of 110 isolates, 28 harbored the clbA gene, 40 harbored clb B, and 24 isolates harboured cnf1. 13 isolates harbored clbA, clbB, and cnf1 genes, while no cnf2 gene was detected among isolates. The molecular detection revealed that 8 out of 28 hemolytic isolates carrying the clbA, 11 out of 40 were carrying clbB, 1 out of 24 were carrying cnf 1, and 5 out of 9 carrying clbA+clbB. Furthermore, 7 out of 13 isolates were hemolytic and carrying clbA, clbB, and cnf1 genes. Finally, we investigated the cytotoxicity of E. coli harboring clb and cnf genes, eukaryotic REF cells were exposed to E. coli producing colibactin, which induces DNA damage and leads to cell cycle arrest, senescence and death.

A RTL Binding Technique for CPLD constraint (CPLD 조건식을 위한 RTL 바인딩)

  • Kim, Jae-Jin;Yun, Choong-Mo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.12
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    • pp.2181-2186
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    • 2006
  • In this paper, a RTL binding technique for CPLD constraint is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in used CLB.

CLB-ECC: Certificateless Blind Signature Using ECC

  • Nayak, Sanjeet Kumar;Mohanty, Sujata;Majhi, Banshidhar
    • Journal of Information Processing Systems
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    • v.13 no.4
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    • pp.970-986
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    • 2017
  • Certificateless public key cryptography (CL-PKC) is a new benchmark in modern cryptography. It not only simplifies the certificate management problem of PKC, but also avoids the key escrow problem of the identity based cryptosystem (ID-PKC). In this article, we propose a certificateless blind signature protocol which is based on elliptic curve cryptography (CLB-ECC). The scheme is suitable for the wireless communication environment because of smaller parameter size. The proposed scheme is proven to be secure against attacks by two different kinds of adversaries. CLB-ECC is efficient in terms of computation compared to the other existing conventional schemes. CLB-ECC can withstand forgery attack, key only attack, and known message attack. An e-cash framework, which is based on CLB-ECC, has also been proposed. As a result, the proposed CLB-ECC scheme seems to be more effective for applying to real life applications like e-shopping, e-voting, etc., in handheld devices.

Airborne particulate matter increases MUC5AC expression by downregulating Claudin-1 expression in human airway cells

  • Kim, Sang-Su;Kim, Cheol Hong;Kim, Ji Wook;Kung, Hsi Chiang;Park, Tae Woo;Shin, Yu Som;Kim, Ju Deok;Ryu, Siejeong;Kim, Wang-Joon;Choi, Yung Hyun;Song, Kyoung Seob
    • BMB Reports
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    • v.50 no.10
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    • pp.516-521
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    • 2017
  • $CLB_{2.0}$, a constituent of PM, induces secretion of multiple cytokines and chemokines that regulate airway inflammation. Specifically, IL-6 upregulates $CLB_{2.0}$-induced MUC5AC and MUC1 expression. Interestingly, of the tight junction proteins examined, claudin-1 expression was inhibited by $CLB_{2.0}$. While the overexpression of claudin-1 decreased $CLB_{2.0}$-induced MUC5AC expression, it increased the expression of the anti-inflammatory mucin, MUC1. $CLB_{2.0}$-induced IL-6 secretion was mediated by ROS. The ROS scavenger N-acetyl-cysteine inhibited $CLB_{2.0}$-induced IL-6 secretion, thereby decreasing the $CLB_{2.0}$-induced MUC5AC expression, whereas $CLB_{2.0}$-induced MUC1 expression increased. $CLB_{2.0}$ activated the ERK1/2 MAPK via a ROS-dependent pathway. ERK1/2 downregulated the claudin-1 and MUC1 expressions, whereas it dramatically increased $CLB_{2.0}$-induced MUC5AC expression. These findings suggest that $CLB_{2.0}$-induced ERK1/2 activation acts as a switch for regulating inflammatory conditions though a ROS-dependent pathway. Our data also suggest that secreted IL-6 regulates $CLB_{2.0}$-induced MUC5AC and MUC1 expression via ROS-mediated downregulation of claudin-1 expression to maintain mucus homeostasis in the airway.

CLB-Based CPLD Low Power Technology Mapping A1gorithm for Trade-off (상관관계에 의한 CLB구조의 CPLD 저전력 기술 매핑 알고리즘)

  • Kim Jae-Jin;Lee Kwan-Houng
    • Journal of the Korea Society of Computer and Information
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    • v.10 no.2 s.34
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    • pp.49-57
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    • 2005
  • In this paper. a CLB-based CPLD low power technology mapping algorithm for trade-off is proposed. To perform low power technology mapping for CPLD, a given Boolean network has to be represented to DAG. The proposed algorithm consists of three step. In the first step, TD(Transition Density) calculation have to be Performed. Total power consumption is obtained by calculating switching activity of each nodes in a DAG. In the second step, the feasible clusters are generated by considering the following conditions : the number of output. the number of input and the number of OR-terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. The proposed algorithm is examined by using benchmarks in SIS. In the case that the number of OR-terms is 5, the experiments results show reduction in the power consumption by 30.73$\%$ comparing with that of TEMPLA, and 17.11$\%$ comparing with that of PLAmap respectively

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Development of CPLD Technology Mapping Algorithm Improving Run-Time under Time Constraint (시간제약 조건하에서 수행시간을 개선한 CPLD 기술 매핑 알고리즘 개발)

  • 윤충모;김희석
    • Journal of the Korea Society of Computer and Information
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    • v.4 no.4
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    • pp.15-24
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    • 1999
  • In this paper, we propose a new CPLD technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result. it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB.

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A RTL Binding Technique and Low Power Technology Mapping consider CPLD (CPLD를 고려한 RTL 바인딩과 저전력 기술 매핑)

  • Kim Jae-Jin;Lee Kwan-Houng
    • Journal of the Korea Society of Computer and Information
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    • v.11 no.2 s.40
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    • pp.1-6
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    • 2006
  • In this paper, a RTL binding technique and low power technology mapping consider CPLD is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD consider low power. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in the power consumption by 43% comparing with that of non application algorithm.

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A CLB based CPLD Low-power Technology Mapping Algorithm (CLB 구조의 CPLD 저전력 기술 매핑 알고리즘)

  • 김재진;윤충모;인치호;김희석
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1165-1168
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    • 2003
  • In this paper, a CLB-based CPLD low-power technology mapping algorithm is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. Therefore the proposed algorithm is proved an efficient algorithm for a low power CPLD technology mapping.

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Development of Technology Mapping Algorithm for CPLD by Considering Time Constraint (시간제약 조건을 고려한 CPLD 기술 매핑 알고리즘 개발)

  • Kim, Hi-Seok;Byun, Sang-Zoon
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.6
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    • pp.9-17
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    • 1999
  • In this paper, we propose a new technology mapping algorithm for CPLD under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces delay time and the number of CLBs much more than the existing tools of technology mapping algoritm.

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A RTL binding technique with CPLD constraint (CPLD 조건식을 고려한 RTL 바인딩)

  • 김재진;윤충모;김희석
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.799-802
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    • 1998
  • 본 논무은 HLS에서 CPLD 조건식을 고려한 RTL바인딩 기술로서 HDL로 기술된 회로의 스케쥴링을 한후 모듈 연산 간격을 고려하여 합당한 모듈을 선택하고 스케쥴링과 할당을 수행한 후 주어진 조건식에 맞도록 CPLD를 선정한다. 또한 할당된 결과의 모듈을 CPLD 내부의 CLB의 크기를 고려하여 부울식을 분할하고 최적의 CLB를 사용하여 회로를 구현할 수 있도록 binding 알고리즘을 제안하였다.

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