• Title/Summary/Keyword: CIC 필터

Search Result 34, Processing Time 0.041 seconds

A Design of Wavelet OFDM based on CIC Filter (CIC 필터를 이용한 Wavelet OFDM 설계)

  • Moon, Ki-Tak;Jang, Dong-Won;Kim, Kyung-Seok
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.36 no.2C
    • /
    • pp.93-98
    • /
    • 2011
  • Currently, The new communication system was very important because of the increasing demand for Internet access. One of these alternatives is the PLC. But, Power Line is not suitable for communication. So, electromagnetic wave is generated from Power Line during flow of communication information. And the electromagnetic wave is interfered with Wireless Communication Service using the same frequency range. To eliminate this interference by used Notch tilter. Wavelet OFDM in another way, while one is used. In this paper, Wavelet OFDM CIC filter used in the CMFB structure by applying a further lowering the value of the side-lobe is proposed to improve performance.

Sigma Delta Decimation Filter Design for High Resolution Audio Based on Low Power Techniques (저전력 기법을 사용한 고해상도 오디오용 Sigma Delta Decimation Filter 설계)

  • Au, Huynh Hai;Kim, SoYoung
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.49 no.11
    • /
    • pp.141-148
    • /
    • 2012
  • A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

Passband Droop and Stopband Attenuation Improvement of Decimation Filters Using Interpolated Fourth-Order Polynomials (4차 보간 필터를 사용한 데시메이션 필터의 통과대역/저지대역 특성 개선)

  • 장영범;이원상;유현중
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.29 no.6C
    • /
    • pp.777-784
    • /
    • 2004
  • In this paper, a new filter structure to improve frequency response characteristics in decimation filter using CIC(Cascaded Integrator-Comb) filters and half band filters is proposed. Conventional filters improve only passband characteristics, but we propose a new filter which can improve stop band and pass band characteristics simultaneously. Since proposed filter needs only two multiplication, additional implementation cost is not much. And overall linear phase characteristics are maintained since the proposed filter is also linear phase. Finally, filter coefficients quantization effects ate discussed after Verilog-HDL coding.

Design and Analysis of Decimation Filers with Minimal Distortion for a High Speed High Performance Sigma-Delta ADC (고속 고성능 시그마-델타 ADC를 위한 최소왜곡 데시메이션 필터의 설계 및 분석)

  • Kang, Ho-jin;Kim, Hyung-won
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.19 no.11
    • /
    • pp.2649-2655
    • /
    • 2015
  • While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

Almost linear-phase compensator for Cascaded Integrator-Comb filter (Cascaded Integrator-Comb 필터를 위한 근사 선형 위상 보상기)

  • Lee Kyu-Ha;Lee Chung-yong
    • Journal of the Institute of Electronics Engineers of Korea SP
    • /
    • v.42 no.4 s.304
    • /
    • pp.153-158
    • /
    • 2005
  • In this paper, a filter is proposed to compensate droop of the CIC filter for SDR. The proposed compensation filter has almost linear-phase characteristic, requires low operational complexity, and is cost-effective due to its second-order characteristic and lowest operational rate in the baseband.. Especially, it compensates droop in the passband with little performance degradation in the stopband. It is shown, by a design example and its performance analysis, that the proposed compensation method gives performance enhancement in communication systems. It is also shown that the proposed method is superior to conventional ones in view of memory usage and computational load.

Design of Low Area Decimation Filters Using CIC Filters (CIC 필터를 이용한 저면적 데시메이션 필터 설계)

  • Kim, Sunhee;Oh, Jaeil;Hong, Dae-ki
    • Journal of the Semiconductor & Display Technology
    • /
    • v.20 no.3
    • /
    • pp.71-76
    • /
    • 2021
  • Digital decimation filters are used in various digital signal processing systems using ADCs, including digital communication systems and sensor network systems. When the sampling rate of digital data is reduced, aliasing occurs. So, an anti-aliasing filter is necessary to suppress aliasing before down-sampling the data. Since the anti-aliasing filter has to have a sharp transition band between the passband and the stopband, the order of the filter is very high. However, as the order of the filter increases, the complexity and area of the filter increase, and more power is consumed. Therefore, in this paper, we propose two types of decimation filters, focusing on reducing the area of the hardware. In both cases, the complexity of the circuit is reduced by applying the required down-sampling rate in two times instead of at once. In addition, CIC decimation filters without a multiplier are used as the decimation filter of the first stage. The second stage is implemented using a CIC filter and a down sampler with an anti-aliasing filter, respectively. It is designed with Verilog-HDL and its function and implementation are validated using ModelSim and Quartus, respectively.

Low-power Heartbeat Detection Algorithm and Structure Using Modified CIC Filter Banks (Modified CIC 필터뱅크를 이용한 저전력 심장박동수 측정 알고리즘 및 구조)

  • Oh, Seung-Lee;Jang, Young-Beom
    • The Transactions of The Korean Institute of Electrical Engineers
    • /
    • v.62 no.2
    • /
    • pp.264-269
    • /
    • 2013
  • In this paper, low-power heart beat detection algorithm and structure is proposed. The proposed detection algorithm utilizes filter banks to display a specific beat per minute(BPM) from the heart beat signals. Since general filter banks need a lot of computation to calculate a BPM, we propose the filter banks structure using modified CIC(Cascaded Integrator Comb) filters. It is shown that the proposed modified CIC filter banks algorithm can display the BPM from the heart beat signals precisely and efficiently.

Decimation Filter Design and Performance Analysis for a High-Speed Sigma-Delta ADC with Minimal Passband Distortion (최소 왜곡의 통과 대역을 가지는 고속 시그마-델타 ADC용 데시메이션 필터의 설계 및 성능 분석)

  • Kang, Ho-jin;Kim, Hyung-won
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2015.10a
    • /
    • pp.405-408
    • /
    • 2015
  • While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure, which is a type of an IIR filter. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

  • PDF

Low-power Digital Down Conversion filter design for Multi-mode (Multi-mode용 저전력 Digital Down Conversion filter 설계)

  • Kim, Do-Han;Hur, Eun-Sung;Jang, Young-Beom
    • Proceedings of the IEEK Conference
    • /
    • 2007.07a
    • /
    • pp.75-76
    • /
    • 2007
  • 이 논문에서는 IS-95와 WCDMA의 Multi-mode로 동작하는 Multi-mode용 저전력 DDC filter 구조를 제안한다. 기존의 DDC구조의 경우 CIC의 통과대역 특성을 향상시켜 주지만, 저지대역의 감쇠특성은 오히려 나빠지는 문제점을 안고 있었다. 제안된 구조는 CIC 데시메이션 필터의 통과대역 특성은 더욱 향상시켜주며, 저지대역의 감쇠특성도 같이 향상시키는 특징을 가진다. 또한 제안된 절터는 각 필터의 면적을 감소시키기 위해 IS-95와 WCDMA의 각각의 모드에 대해 한 개의 필터를 설계한 후 각 모드에 따라 필터 탭 수를 달리하여 동작하는 Multi-mode의 저전력 구조로 구현하였다.

  • PDF

The Implementation of DDC for the WLAN Receiver (WLAN 수신기를 위한 Digital Down Converter (DDC) 구현)

  • Jeong, Kil-Hyun
    • Journal of the Korea Society of Computer and Information
    • /
    • v.17 no.2
    • /
    • pp.113-118
    • /
    • 2012
  • In this paper, we discuss the design of the Digital Down Converters for the IEEE 802.11 wireless LAN receiver, which can be used for the customized receiver. The customized receiver can be used for special puropsed services which cannot be realized using the general custom chip. In the OFDM receiver, DDC receives the up sampled Inphase/Quadrature signal from the AD converter and process down sampling and filtering procedures using the Cascaded Intergrator Filter and FIR filters. We discuss the structure and design methodology of DDC's and analyze the simulation results.