• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.26-32
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• 2008

The conventional shared bus architecture is capable of processing only one data transaction in same time. In this paper, we propose the NAWM (No Arbitration Wild Master) bus architecture that is capable of processing several data transactions in same time. After designing the master and the slave wrappers of NAWM bus architecture about AMBA system, we confirm that most of IPs of AMBA system can be a lied without modification and the added timing delay can be neglected. from simulation we deduce that more than 50% parallel processing is possible when several masters initiate slaves in NAWM bus architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.50-56
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• 2009

SoC(System on a Chip) has several masters, slaves, arbiter and decoder in bus architecture. Master initiates the data transactions like CPU, DMA and DSP and slave responses the data transactions like SRAM SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, SoC performance can be changed definitely. Fixed priority, round-robin, TDM arbitration are used in general arbitration method, In this study, we compose TLM algorithm and analyze general arbitration methods through TLM simulation. Consequently, we propose the hybrid bus arbitration policy and verify the performance, compared with the other arbitration methods.

• Transactions on Electrical and Electronic Materials
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• v.17 no.1
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• pp.1-6
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• 2016

Ensuring the secure operation of power systems has become an important and critical matter during the present time, along with the development of large, complex and load-increasing systems. Security constraints such as the thermal limits of transmission lines and bus-voltage limits must be satisfied under all of a system’s operational conditions. An alternative solution to improve the security of a power system is the employment of Flexible Alternating-Current Transmission Systems (FACTS). FACTS devices can reduce the flows of heavily loaded lines, maintain the bus voltages at desired levels, and improve the stability of a power network. The Unified Power Flow Controller (UPFC) is a versatile FACTS device that can independently or simultaneously control the active power, the reactive power and the bus voltage; however, to achieve such functionality, it is very important to determine the optimal location of the UPFC device, with the appropriate parameter setting, in the power system. In this paper, a genetic algorithm (GA) method is applied to determine the optimal location of the UPFC device in a network for the enhancement of the power-system loadability and the minimization of the active power loss in the transmission line. To verify our approach, simulations were performed on the IEEE 14 Bus, 30 Bus, and 57 Bus test systems. The proposed work was implemented in the MATLAB platform.

• Transactions of the Korean hydrogen and new energy society
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• v.33 no.5
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• pp.463-469
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• 2022

After reviewing the current status of hydrogen buses and hydrogen charging stations in the United States, as well as related laws and programs, it was found that the federal and state governments supported the supports of hydrogen buses and the deployment of hydrogen charging infrastructure through various policies and programs. In order to promote the spread of domestic and overseas hydrogen buses and hydrogen charging infrastructure, it is necessary to develop and apply various legal systems and programs that can provide incentives to hydrogen bus manufacturers, hydrogen charging station installers, hydrogen bus operating organizations and entities. It is necessary to develop and apply various legal systems and programs that can provide incentives to hydrogen bus manufacturers, hydrogen charging station installers, hydrogen bus operating organizations and entities.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.224-240
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• 1996

It is common sense for at least one or more levels of cache memory to be used in these day's computer systems. In this paper, the impact of the internal cache memory organization on the performance of the computer is investigated by using a simulator program, which is wirtten by authors and run on SUN SPARC workstation, with several real execution, with several real execution trace files. 280 cache organizations have been simulated using n-way set associative mapping and LRU(Least Recently Used) replacement algorithm with write allocation policy. As a result, 16-way setassociative cache is the best configuration, and when we select 256KB cache memory and 64 byte line size, the bus traffic ratio was decreased compared to that of the noncache system so that a single bus could support almost 7 processors without any delay and degradationof high ratio(hit ratio was 99.21%). The smaller the line size we choose, the little lower hit ratio we can get, but the more processors can be supported by a single bus(maximum 18 processors). Therefore, using a proper cache memory organization can make a single bus structure be able to support multiple processors without any performance degradation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.1-6
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• 2009

This paper presents new high speed architecture using DBI(Data Bus Inversion) in DRAM. The DBI is one of the general methods in the signaling circuits to decrease the known problems such as SSO and LSI. Many architectures have been proposed to reduce the number of transitions on the data bus. In this paper, the DBI, the Analog Majority Voter (AMV) circuit, the GIO control circuit and the SSO algorithm are newly proposed. The power consumption can he reduced with the help of direct GIO inversion method and the eye diagram of data can be increased to 40ps. Using proposed DBI scheme can produce almost stable SI of DQs against high speed operation. The DBI is fabricated in 90nm CMOS Technology.

• Journal of the Semiconductor & Display Technology
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• v.15 no.4
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• pp.61-66
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• 2016

This paper presents the implementation for a network structure of railway cars using a point to point communication. Most of network's representative specifications for a train are the FIP (Field Bus), MVB (Multifunction Vehicle Bus), CAN and WTB (Wire Train Bus) which is used by ALSOM, SIEMENS and BOMBADIER as major in this field. These networks in a physical layer use a multi-drop method, connected from $1^{st}$ car to $n^{th}$ car of a train through a cable without any extra services such as an electric part, amplifier. However waveforms which is passed through a long cable in the multi-drop are distorted by a capacitance or resistance of the cable or environments. Also since using a cable connected directly from $1^{st}$ car to $n^{th}$ car, if over two trains make double head, it isn't easy to distinguish ID for each railway cars. So by using the point to point network per each car, it is able to reduce a distortion. Also since reducing distortion, this communication speed can be been higher and transmit and receive any packets more stably. Using proposed token in a packet, this can make ID per each railway car automatically. Finally experimental results show the good performance and effectiveness of the proposed method.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.7
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• pp.10-16
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• 1999

This paper describes a low voltage swing bus driver using FCSR(Feedback Control Swing voltage Reduction) which can control bus swing voltage within a few hundred of mV. It is proposed to reduce power consumption in On-chip interface, especially for MDL(Merged DRAM Logic) architecture wihich has wide and large capacitance bus. FCSR operates on differential signal dual-line bus and on precharged bus with block controlling fuction. We modeled driver and bus to scale driver size automatically when bus environment is variant. We also modeled coupling capacitance noise(crosstalk) of neighborhood lines which operate on odd mode with parallel current source to analysis crosstalk effect in the victim-line according as voltage transition in the aggressor-line and environment in the victim-line. We built a test chip which was designed to swing 600mV in bus, shows 70Mhz operation at 3.3V, using Hyundai 0.8um CMOS technology. FCSR operate with 250Mhz at 3.3V by Hspice simulation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.12
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• pp.5838-5842
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• 2011

The study mainly aims to explore how deterioration of motor control center, namely MCC, and vibration put impact on temperature of bus bar as well as temperature change of bolt-nut joint. The motor control center consists of three internal parts (i.e. R, S, T) which are for motor operation of high capacity. Two dimensional mechanism for measuring temperature was designed and manufactured with infrared temperature sensor. Installing it in inner motor control center enabled researcher to monitor temperature of bus bar as well as amount of change of current regularly. Temperature change of bus bar according to load was primarily examined based on a bolted joint in the experiment. It was clearly verified that temperature change of bus bar was proportional to current consumption. Therefore, installing non-contact two dimensional mechanism for measuring temperature in motor control center would be expected to prevent temperature rise owing to overload current and power outage as well as fire accident which can be triggered by poor electrical contact.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.21 no.1
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• pp.35-50
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• 2022

After the introduction of the central bus lane system, bus traffic was prioritized. This resulted in improved trust from bus users. However, the low capacity at the central bus stop reduces traffic speed and punctuality. In addition, physical constraints are inevitable because the construction of central bus lanes and bus stops considers the city's road geometry. Therefore, this study attempted to optimize the effective green time of the traffic signal system at the entrance and exit of the central bus stop to remedy its insufficient operational capacity. The Transit Capacity and Quality of Service Manual and Korea Highway Capacity Manual were used as the analysis methodologies. The number of stop areas for central bus stops to be built was determined by excluding variable physical factors, and field survey data collected from nine randomly selected central bus stops currently installed in Seoul were used. A scenario analysis was conducted on the central bus stops with insufficient capacity by adjusting the effective green time, and the capacity of the central bus stop was set as the dependent variable. According to the results, 26.7 percent of the central bus stops with insufficient capacity can solve the problem of insufficient capacity. Therefore, the results of this study can be verified by improving the operation level, and it can be effective even if the number of central bus stops calculated by engineering is not guaranteed during the planning stage of the central bus stop. As the number of central bus stops is expected to increase further as the number of central bus stops increases, it is necessary to improve the number of central bus stops. Therefore, it is hoped that the results presented in this study will be used as basic data for the improvement plan at the operational level before introducing the physical improvement plan.