• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.27.1-27.1
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• 2011

The recent extensive research of one-dimensional (1D) nanostructures such as nanowires (NWs) and nanotubes (NTs) has been the driving force to fabricate new kinds of nanoscale devices in electronics, optics and bioengineering. We attempt to produce silicon oxide nanowires (SiOxNWs) in a simple way without complicate deposition process, gaseous Si containing precursors, or starting material of $SiO_2$. Nickel (Ni) nanoparticles (NPs) were applied on Si wafer and thermally treated in a furnace. The temperature in the furnace was kept in the ranges between 900 and $1,100^{\circ}C$ and a mixture of nitrogen ($N_2$) and hydrogen ($H_2$) flowed through the furnace. The SiOxNWs had widths ranging from 100 to 200 nm with length extending up to ~10 ${\mu}m$ and their structure was amorphous. Ni NPs were acted as catalysts. Since there were no other Si materials introduced into the furnace, the Si wafer was the only Si sources for the growth of SiOxNWs. When the Si wafer with deposition of Ni NPs was heated, the liquid Ni-Si alloy droplets were formed. The droplets as the nucleation sites induce an initiation of the growth of SiOxNWs and absorb oxygen easily. As the droplets became supersaturated, the SiOxNWs were grown, by the reaction between Si and O and continuously dissolving Si and O onto NPs. Photoluminescence (PL) showed that blue emission spectrum was centered at the wavelength of 450 nm (2.76 eV). The details of growth mechanism of SiOxNWs and the effect of Ni NPs on the formation of SiOxNWs will be presented.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.115-121
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• 2002

In this research we have investigated the characteristics of ultra thin $HfO_2 /SiON$stack structure films using several analytical techniques. SiON layer was thermally grown on standard SCI cleaned silicon wafer at $825^{\circ}C$ for 12sec under $N_2$O ambient. $HfO_2 /SiON$$_4$/$H_2O$ as precursors and $N_2$as a carrier/purge gas. Solid HfCl$_4$was volatilized in a canister kept at $200^{\circ}C$ and carried into the reaction chamber with pure $N_2$carrier gas. $H_2O$ canister was kept at $12^{\circ}C$ and carrier gas was not used. The films were grown on 8-inch (100) p-type Silicon wafer at the $300^{\circ}C$ temperature after standard SCI cleaning, Spectroscopic ellipsometer and TEM were used to investigate the initial growth mechanism, microstructure and thickness. The electrical properties of the film were measured and compared with the physical/chemical properties. The effects of heat treatment was discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.217-221
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• 2004

[ $CO_2$ ]laser ablation rates for bulk 4H-SiC substrates and GaN/AIN/SiC templates in the range 229-870 ${\mu}m.min^{-1}$ were obtained for pulse energies of 7.5-30 mJ over diameters of 50·500 ${\mu}m$ with a Q-switched pulse width of ${\sim}30$ nsec and a pulse frequency of 8 Hz. The laser drilling produces much higher etch rates than conventional dry plasma etching (0.2 - 1.3 ${\mu}m/min$) making this an attractive maskless option for creating through-wafer via holes in SiC or GaN/AlN/SiC templates for power metal-semiconductor field effect transistor applications. The via entry can be tapered to facilitate subsequent metallization by control of the laser power and the total residual surface contamination can be minimized in a similar fashion and with a high gas throughput to avoid redeposition. The sidewall roughness is also comparable or better than conventional via holes created by plasma etching.

• 한국재료학회지
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• 제16권10호
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• pp.652-655
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• 2006

A direct wafer bonding process necessary for GaAs-on-insulator (GOI) fabrication with high thermal annealing temperatures was studied by using PECVD oxides between gallium arsenide and silicon wafers. In order to apply some uniform pressure on initially-bonded wafer pairs, a graphite sample holder was used for wafer bonding. Also, a tool for measuring the tensile forces was fabricated to measure the wafer bonding strengths of both initially-bonded and thermally-annealed samples. GaAs/$SiO_2$/Si wafers with 0.5-$\mu$m-thick PECVD oxides were annealed from $100^{\circ}C\;to\;600^{\circ}C$. Maximum bonding strengths of about 84 N were obtained in the annealing temperature range of $400{\sim}500^{\circ}C$. The bonded wafers were not separated up to $600^{\circ}C$. As a result, the GOI wafers with high annealing temperatures were demonstrated for the first time.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.374-375
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• 2006

This paper describes anodic bonding characteristics of MCA to Si-wafer using evaporated Pyrex #7740 glass thin-films for MEMS applications. Pyrex #7740 glass thin-films with the same properties were deposited on MCA under optimum RF sputter conditions (Ar 100 %, input power $1\;W/cm^2$). After annealing at $450^{\circ}C$ for 1 hr, the anodic bonding of MCA to Si-wafer was successfully performed at 600 V, $400^{\circ}C$ in $110^{-6}$ Torr vacuum condition. Then, the MCA/Si bonded interface and fabricated Si diaphragm deflection characteristics were analyzed through the actuation and simulation test. It is possible to control with accurate deflection of Si diaphragm according to its geometries and its maximum non-linearity being 0.05-0.08 %FS. Moreover, any damages or separation of MCNSi bonded interfaces did not occur during actuation test. Therefore, it is expected that anodic bonding technology of MCNSi-wafers could be usefully applied for the fabrication process of high-performance piezoelectric MEMS devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• KSTLE International Journal
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• 제5권2호
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• pp.37-43
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• 2004

Abstract : Nano/micro-scale friction properties were investigated on Si (100) and three self-assembled monolayers (SAMs) (PFOTC, DMDM, DPDM) coated on Si-wafer by chemical vapor deposition technique. Experiments were conducted at ambient temperature(24$pm$1$circ$C) and humidity(45$pm$5%). Friction at nano-scale was measured using Atomic Force Microscopy (AFM) in the range of 0-40nN normal loads. In both Si-wafer and SAMs, friction increased linearly as a function of applied normal load. Results showed that friction was affected by the inherent adhesion in Ssi-wafer, and in the case of SAMs the physical/chemical structures had a major influence. Coefficient of friction of these test samples at the micro-scale was also energies. In order to study the effect of contact area on coefficient of friction at the micro-scale, friction was measured for Si-wafer and DPDM against Soda Lime balls (Duke Scientiffic Corporation) of different radii (0.25 mm, 0.5 mm and 1 mm) at different applied normal loads (1500, 3000 and 4800 mN). Results showed that Si-wafer had higher coefficient of friction than DPDM. Further, unlike that in the case of DPDM, friction in Si-wafer was severely influenced by its wear. SEM evidences showed that solid-solid adhesion was the wear mechanism in Si-wafer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.164-167
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• 2002

SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS applications because of its application possibility in harsh environments. This paper presents on pre-bonding according to HF pre-treatment conditions in SiC wafer direct bonding using PECVD oxide. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, and applied pressure. The 3C-SiC epitaxial films grown on Si(100) were characterized by AFM and XPS, respectively. The bonding strength was evaluated by tensile strength method. Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding (Min : 5.3 kgf/$\textrm{cm}^2$∼Max : 15.5 kgf/$\textrm{cm}^2$).

• 자원리싸이클링
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• 제12권3호
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• pp.25-30
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• 2003

본 연구의 목적은 실리콘웨이퍼의 절단공정에서 발생한 폐슬러리와 폐망간전지에서 발생하는 흑연봉을 각각 규소 및 탄소의 출발물질로 사용하여 가스터빈 부품, 열교환기 등에 사용되는 탄화규소(SiC)를 합성하는 연구를 수행하였다. 실리콘웨이퍼의 절단공정에서 발생하는 폐슬러리로부터 비중차이에 의한 선별과 자력선별 등에 의해 정제된 규소와 탄화규소를 얻을 수 있었으며, 폐망간전지를 해체하여 얻은 탄소봉으로부터 수세와 분쇄를 통하여 탄소분말을 얻을 수 있었다. 탄화규소의 합성은 규소와 당량비의 탄소분발을 혼합하여 1$600^{\circ}C$이상의 온도에서 아르곤 분위기와 진공분위기 하에서 2시간 유지시켰을 때 이루어졌으며, 이때 합성된 탄화규소의 순도는 99% 이상이었다.

• 한국진공학회지
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• 제6권1호
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• pp.9-19
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• 1997

본 연구에서는 실리콘 웨이퍼 표면에 존재하는 미량의 Zn, Fe, Ti 금속 오염물들이 UV-excited chlorine radical을 이용한 건식세정 방법으로 제거되는 반응과정을 찾아내고자 하였다. 실리콘 웨이퍼 상에 진공증착법으로 원형패턴이 있는 Zn, Fe, Ti 박막을 증착시켜 상온 및 $200^{\circ}C$에서 UV/$Cl_2$세정하였을 때, 염소 래디컬($Cl^*$)이 Fe, Zn, Ti와 반응하여 제거되 는 것을 반응 전후 광학현미경과 SEM을 통해 표면 형상 변화를 관찰하였고, in-line으로 연결된 XPS를 통해서 반응 후 웨이퍼 표면에 남아있는 화합물의 화학적 결합상태를 관찰 하였으며, UV/$Cl_2$ 세정 후 실리콘 기판이 손상받는 정도를 알기 위해 AFM으로 표면 거칠 기를 측정하였다. 광학현미경과 SEM의 분석 결과에 의하면 Zn와 Fe는 쉽게 제거되는 반면 염화물을 형성하기 보다는 휘발성이 적은 산화물을 형성하는 경향이 강한 Ti은 약간만 제 거되는 것을 확인하였다. XPS분석을을 통해서 이들 금속 오염물들이 chlorine radical과 반 응하여 웨이퍼 표면에 금속 염화물을 형성하고 있는 것을 확인하였고, UV/$Cl_2$세정처리를 하였을 때 실리콘 웨이퍼의 표면 거칠기가 약간 증가하는 것을 알 수 있었다. 지금까지의 결 과를 볼 때, 습식세정과 UV/$Cl_2$건식세정을 병행하면 플라즈마 및 레이저를 사용하는 다른 건식세정 방법에 비하여 보다 저온에서 실리콘 기판의 큰 손상 없이 비교적 용이하게 금속 오염물을 제거할 수 있음을 제안 하였다.