• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.390-390
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• 2010

Superconducting proximity effects of Nb/Si(111) were investigated with scanning tunneling microscopy(STM) and scanning tunneling spectroscopy(STS). A highly-doped($0.002\;{\omega}{\diamondsuit}cm$) Si wafer pieces were used as substrate and Nb source was thermally evaporated onto the atomically clean silicon substrate. The temperature of the silicon sample was held at $600^{\circ}C$ during the niobium deposition. And the sample was annealed at $600^{\circ}C$ for 30 minutes additionally. Volmer-Weber growth mode is preferred in Nb/Si(111) at the sample temperature of $600^{\circ}C$. With proper temperature and annealing time, we can obtain Nb islands of lateral size larger than Nb coherence length(~38nm). And outside of the islands, bare Si($7{\times}7$) reconstructed surface is exposed due to the Volmer-Weber Growth mode. STS measurement at 5.6K showed that Nb island have BCS-like superconducting gap of about 2mV around the Fermi level and the critical temperature is calculated to be as low as 6.1K, which is lower than that of bulk niobium, 9.5K. This reduced value of superconducting energy gap indicates suppression of superconductivity in nanostructures. Moreover, the superconducting state is extended out of the Nb island, over to bare Si surface, due to the superconducting proximity effect. Spatially-resolved scanning tunneling spectroscopy(SR-STS) data taken over the inside and outside of the niobium island shows gradually reduced superconducting gap.

• Journal of the Korean institute of surface engineering
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• v.49 no.3
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• pp.301-306
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• 2016

The effects of nanotexturing and post-etching on the reflection and quantum efficiency properties of diamond wire sawn (DWS) multicrystalline silicon (mc-Si) solar cell have been investigated. The chemical solutions, which are acidic etching solution (HF-$HNO_3$), metal assisted chemical etching (MAC etch) solutions ($AgNO_3$-HF-DI, HF-$H_2O_2$-DI) and post-etching solution (diluted KOH at $80^{\circ}C$), were used for micro- and nano-texturing at the surface of diamond wire sawn (DWS) mc-Si wafer. Experiments were performed with various post-etching time conditions in order to determine the optimized etching condition for solar cell. The reflectance of mc-Si wafer texturing with acidic etching solution showed a very high reflectance value of about 30% (w/o anti-reflection coating), which indicates the insufficient light absorption for solar cell. The formation of nano-texture on the surface of mc-Si contributed to the enhancement of light absorption. Also, post-etching time condition of 240 s was found adequate to the nano-texturing of mc-Si due to its high external quantum efficiency of about 30% at short wavelengths and high short circuit current density ($J_{sc}$) of $35.4mA/cm^2$.

• Journal of the Korean Ceramic Society
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• v.36 no.2
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• pp.203-209
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• 1999

LaAlO3d single phase used as the butter layer on Si wafer for YBa2Cu3O7-$\delta$ superconductor application were prepared by solid state reaction method and by self-sustaining combustion process. The microstructure and crystallity of synthesiszed LaAlO3 powder studied using scanning electron microscope (SEM) and X-ray diffractometer(XRD), specific surface area and sintering characteristics fo powder were investigated by Brunauer-Emmett-Teller (BET) method and dilatometer respectively. In solid state reaction method, it is difficult to obtain LaAlO3 single phase up to 150$0^{\circ}C$ period. However, in self-sustaining combustion process, it is to easy to do it only $650^{\circ}C$. Based on the results of analysis of dilatometer it is easier to obtain high sintering density (98.87%) in self-sustaining combustion process than in the solid state reaction method. This reason is that the average particle size prepared by self-sustaining combustion process is nano crystal size and has high specific surface are value(56.54 $m^2$/g) compared with that by solid state reaction method. Also, LaAlO3 layer on the Si wafer has been achieved by screen printing and sintering method. Even though the sintering temperature is 130$0^{\circ}C$, the phenomena of silicon out diffusion in LaAlO3/Si interphase are not observed.

• Clean Technology
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• v.24 no.3
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• pp.157-165
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• 2018

In this study, the removal of $Si_3N_4$ particles from the surface of a silicon wafer was investigated by using supercritical carbon dioxide, the IPA co-solvent and cleaning additive chemicals. First, the solubility of several surfactants and binders in supercritical carbon dioxide solubility and particle dispersibility in the binders were evaluated in order to confirm their suitability for the supercritical cleaning process. Particle removal experiments were carried out with adjusting various process parameters and reaction conditions. The surfactants used in the experiment showed little particle removal effect, producing secondary contamination on the surface of wafers. On the other hand, 5 wt% (with respect to $scCO_2$) of the cleaning additive mixture of trimethyl phosphate, IPA, and trace HF resulted in 85% of particle removal efficiency after $scCO_2$ flowing for 4 minutes at $50^{\circ}C$, 2000 psi, and the flow rate of $15mL\;min^{-1}$.

• Current Applied Physics
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• v.18 no.11
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• pp.1436-1440
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• 2018

SiN and SiCN film production using plasma-enhanced atomic layer deposition (PE-ALD) is investigated in this study. A developed high-power and high-density multiple inductively coupled plasma (multi-ICP) source is used for a low temperature PE-ALD process. High plasma density and good uniformity are obtained by high power $N_2$ plasma discharge. Silicon nitride films are deposited on a 300-mm wafer using the PE-ALD method at low temperature. To analyze the quality of the SiN and SiCN films, the wet etch rate, refractive index, and growth rate of the thin films are measured. Experiments are performed by changing the applied power and the process temperature ($300-500^{\circ}C$).

• Journal of the Korean Ceramic Society
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• v.48 no.2
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• pp.189-194
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• 2011

Metallurgical grade silicon was recovered from slurry waste for ingot sawing process by acid leaching and thermal treatment. SiC abrasive was removed by gravity concentration and centrifugation. Metal impurities were removed by the acid leaching using HF/HCl. The remaining SiC was separated by the thermal treatment at $1600^{\circ}C$ in an inert atmosphere by the difference in melting points. The purity of the obtained silicon was found to be around 99.7%.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.53.2-53.2
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• 2010

In this study, we focused on our specialized electrode process for Si back-contact crystalline solar cell. It is different from other well-known back-contact cell process for thermal aspect and specialized process. In general, aluminum makes ohmic contact to the Si wafer and acts as a back surface reflector. And, silver is used for low series resistance metal grid lines. Aluminum was sputtered onto back side of wafer. Next, silver is directly patterned on the wafer by screen printing. The sputtered aluminum was removed by wet etching process after rear silver electrode was formed. In this process, the silver paste must have good printability, electrical property and adhesion strength, before and after the aluminum etching process. Silver paste also needs low temperature firing characteristics to reduce the thermal budget. So it was seriously collected by the products of several company of regarding low temperature firing (below $250^{\circ}C$) and aluminum etching endurance. First of all, silver pastes for etching selectivity were selected to evaluate as low temperature firing condition, electrical properties and adhesive strength. Using the nano- and micron-sized silver paste, so called hybrid type, made low temperature firing. So we could minimize the thermal budget in metallization process. Also the adhesion property greatly depended on the composition of paste, especially added resin and inorganic additives. In this paper, we will show that the metallization process of back-contact solar cell was realized as optimized nano-paste characteristics.

• Journal of IKEEE
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• v.22 no.2
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• pp.427-431
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• 2018

This research was worked about $Ga_2O_3$ Epi wafer that was one of the mose wide band gap semiconductors to be used power semiconductor industry. This wafer was grown $5.3{\mu}m$ thickness on Sn doped $Ga_2O_3$ Substrate by HVPE(Hydride Vapor Phase Epitaxy). Generally, we can fabricate 600V class power semiconductor devices when the thickness of compoound power semiconductor is $5{\mu}m$. but in case of $Ga_2O_3$ Epi wafer, we can obtain over 1000V class. As a result of J-V measurment of the grown $Ga_2O_3$ Epi wafer, we obtain $2.9-7.7m{\Omega}{\cdot}cm^2$ on resistance. Specially, in case of reverse, we comfirmed a little leakage current when the reverse voltage is over 200V.

• Electrical & Electronic Materials
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• v.10 no.10
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• pp.1029-1033
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• 1997

A prototype MFSFET using ferroelectric fluoride BaMgF$_4$as a gate insulator has been successfully fabricated with the help of 2 sheets of metal mask. The fluoride film was deposited in an ultrai-high vacuum system at a substrate temperature of below 30$0^{\circ}C$ and an in-situ post-deposition annealing was conducted for 20 seconds at $650^{\circ}C$ in the same chamber. The interface state density of the BaMgF$_4$/Si(100) interface calculated by a MFS capacitor fabricated on the same wafer was about 8$\times$10$^{10}$ /cm$^2$.eV. The I$_{D}$-V$_{G}$ characteristics of the MFSFET show a hysteresis loop due to the ferroelectric nature of the BaMgF$_4$film. It is also demonstrated that the I$_{D}$ can be controlled by the “write” plus which was applied before the measurements even at the same “read”gate voltage.ltage.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.454-454
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• 2014

Silicon microwire array is one of the promising platforms as a means for developing highly efficient solar cells thanks to the enhanced light trapping efficiency. Among the various fabrication methods of microstructures, deep reactive ion etching (DRIE) process has been extensively used in fabrication of high aspect ratio microwire arrays. In this presentation, we show precisely controlled Si microwire arrays by tuning the DRIE process conditions. A periodic microdisk arrays were patterned on 4-inch Si wafer (p-type, $1{\sim}10{\Omega}cm$) using photolithography. After developing the pattern, 150-nm-thick Al was deposited and lifted-off to leave Al microdisk arrays on the starting Si wafer. Periodic Al microdisk arrays (diameter of $2{\mu}m$ and periodic distance of $2{\mu}m$) were used as an etch mask. A DRIE process (Tegal 200) is used for anisotropic deep silicon etching at room temperature. During the process, $SF_6$ and $C_4F_8$ gases were used for the etching and surface passivation, respectively. The length and shape of microwire arrays were controlled by etching time and $SF_6/C_4F_8$ ratio. By adjusting $SF_6/C_4F_8$ gas ratio, the shape of Si microwire can be controlled, resulting in the formation of tapered or vertical microwires. After DRIE process, the residual polymer and etching damage on the surface of the microwires were removed using piranha solution ($H_2SO_4:H_2O_2=4:1$) followed by thermal oxidation ($900^{\circ}C$, 40 min). The oxide layer formed through the thermal oxidation was etched by diluted hydrofluoric acid (1 wt% HF). The surface morphology of a Si microwire arrays was characterized by field-emission scanning electron microscopy (FE-SEM, Hitachi S-4800). Optical reflection measurements were performed over 300~1100 nm wavelengths using a UV-Vis/NIR spectrophotometer (Cary 5000, Agilent) in which a 60 mm integrating sphere (Labsphere) is equipped to account for total light (diffuse and specular) reflected from the samples. The total reflection by the microwire arrays sample was reduced from 20 % to 10 % of the incident light over the visible region when the length of the microwire was increased from $10{\mu}m$ to $30{\mu}m$.