• 한국세라믹학회지
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• 제33권5호
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• pp.572-582
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• 1996

전류밀도, 70mA/cm2와 전류인가시간, 5초, 10초 조건의 양극반응으로 다공성 실리콘을 제작하여 800~110$0^{\circ}C$에서 열산화시킨 후 AI 전극을 증착시켜 만든 MOS(Metal Oxide Semiconductor) 구조의 C-V(Capacilance-Voltage) 특성을 조사하였다. 800, 90$0^{\circ}C$의 저온과 20~30분 이내의 단시간 산화에서는 산화막의 유전상수가 보통의 열산화막보다 크게 나타나고, 산화온도가 110$0^{\circ}C$의 고온과 60분 이상의 장시간 산화의 경우에는 3.9에 근접한 값을 갖는다. 이는 다공성 실리콘 산화막내에 존재하는 산화되지 않은 silicon들에 의한 효과와 표면적 증가에 의한 정전용량의 증가 효과가 복합적으로 작용하는 것이 그 원인이라 생각된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.551-554
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• 2000

The stability of $Pr_6$$O_{11}$-based ZnO varistors doped with $Y_2$$O_3$ was investigated under various d.c. stresses. The varistors were sintered at $1350^{\circ}C$ for 1h in the addition range of 0.0 to 4.0 mol% $Y_2$$O_3$. The varistors doped with $Y_2$$O_3$ exhibited much higher nonlinearity than that without $Y_2$$O_3$. In Particular, the varistors containing 0.5 mol% $Y_2$$O_3$ showed very excellent V-I characteristics, which the nonlinear exponent was 51.19 and the leakage current was 1.32 $\mu\textrm{A}$. And these varistors also showed an excellent stability, which the variation rate of the varistor voltage and the nonlinear exponent were -0.80% and -2.17%, respectively, under 4th d.c. stress, such as (0.80 $V_ {1mA}$/$90^{\circ}C$/12h)+(0.85 $V_{1mA}$/$115^{\circ}C$/12h)+(0.90 $V_{1mA}$/$120^{\circ}C$/12h)+(0.95 $V_{1mA}$/$125^{\circ}C$/12h). Consequently, since $Pr_ 6$$O_{11}$-based ZnO varistors doped with 0.5 mol% $Y_2$$O_3$ have an excellent stability as well as good nonlinearity, it is expected to be usefully used to develop the superior varistors in future.

• 한국전기전자재료학회논문지
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• 제18권11호
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• pp.977-982
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• 2005

Al/AlN/n-type 6H-SiC (0001) MIS structures were prepared by AlN layers on vicinal 6H-SiC(0001) substrates with reactive RF magnetron sputtering method. The AlN films were annealed at $900^{\circ}C$, $N_2$ atmosphere lot 1 minutes showed the best result. With XRD analysis, AlN(0002) peak was clearly found. The typical dielectric constant value of the AlN film in the MIS capacitors was obtained as 8.4 from photo C-V. Also, the gate leakage current density of the MlS capacitor was $10^{-10}\;A/cm^2$ order within the electric field of 1.8 MV/cm. Finally, the amount of interface trap densities, $D_{it}$, was evaluated as $5.3\times10^{10}\;eV^{-1}cm^{-2}$ at (Ec-0.85) eV.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.343-347
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• 2004

High oxidation temperature of SiC shows a tendency of carbide formation at the interface which results in poor MOSFET transfer characteristics. Thus we developed oxidation processes in order to get low interface charge densities. N-type 6H-SiC MOS capacitors were fabricated by different oxidation processes: dry, wet, and dry­reoxidation. Gate oxidation and Ar anneal temperature was $1150^{\circ}C.$ Ar annealing was performed after gate oxidation for 30 minutes. Dry-reoxidation condition was $950^{\circ}C,$ H2O ambient for 2 hours. Gate oxide thickness of dry, wet and dry-reoxidation samples were 38.0 nm, 38.7 nm, 38.5 nm, respectively. Mo was adopted for gate electrode. To investigate quality of these gate oxide films, high frequency C- V measurement, gate oxide leakage current, and interface trapped charge densities (Dit) were measured. The interface trapped charge densities (Dit) measured by conductance method was about $4\times10^{10}[cm^{-1}eV^{-1}]$ for dry and wet oxidation, the lowest ever reported, and $1\times10^{11}[cm^{-1}eV^{-1}]$ for dry-reoxidation

• 대한화학회지
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• 제50권1호
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• pp.7-13
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• 2006

모양의 캘릭스[4]아릴에스터 호스트(1)와 그것의 알칼리 금속 양이온과의 착물에 대하여 이론적인 적외선 흡수 스펙트럼들이 계산되었다. 진동 스펙트럼들은 RHF/6-31G 방법으로 최적화 된 후에 얻어졌다. 1+Na+ 착물의 여러 가지 C-O와 C=O 신축 운동들의 특징적인 진동수들은 C2v 형태의 분자 모양을 입증하여 주는 데에 반하여, 1+K+ 착물의 구조는 C4v에 가깝다는 것을 보여 주었다. 호스트 분자(1)와 1+Na+ 착물에 대한 이론적인 결과와 실험 스펙트럼들을 비교하였을 때, 계산된 진동수들이 실험 데이터와 잘 일치하는 것을 알 수 있었다.

• ETRI Journal
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• 제44권5호
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• pp.859-874
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• 2022

This paper presents a low-power and lightweight human body communication (HBC) receiver with an embedded dummy electrode for improved signal acquisition. The clock data recovery (CDR) circuit in the receiver operates with a low supply voltage and utilizes a clock phase inversion scheme. The receiver is equipped with a main electrode and dummy electrode that strengthen the capacitive-coupled signal at the receiver frontend. The receiver CDR circuit exploits a clock inversion scheme to allow 0.9-V operation while achieving a shorter lock time than at 3.3-V operation. In experiments, a receiver chip fabricated using 130-nm complementary metal-oxide-semiconductor technology was demonstrated to successfully receive the transmitted signal when the transmitter and receiver are placed separately on each hand of the user while consuming only 4.98 mW at a 0.9-V supply voltage.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 추계종합학술대회
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• pp.200-203
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• 2007

넓은 에너지 갭의 물질인 탄화규소(4H)기판을 사용하여, 초고내압을 위한 접합장벽 쇼트키 구조의 소자를 설계하여 제작하였다. 측정결과로써 소자의 역방향 I-V 특성은 1000V 이상의 항복전압을 보였고 p-grid의 설계 최적 길이는 $3{\mu}m$ 간격이였다. 이 연구에서는 제작한 소자의 공정 조건 파라미터들을 사용하여 I-V 특성을 모델링 하였고 I-V 특성 파라미터들을 추출하여 실제 소자 파라미터와 비교, 분석하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집
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• pp.47-52
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• 2004

$HgGa_2S_4$ single crystals were grown by the chemical transport reaction method. The $HgGa_2S_4$ single crystal crystallized into a defect chalcopyrite structure $(I\bar{4})$. The lattice constants of the single crystal were found to be a=5.635 ${\AA}$ and c=10.473 ${\AA}$. The direct and indirect optical energy gaps were found to be 2.84 eV and 2.78 eV, respectively. Photoluminescence peaks of $HgGa_2S_4$ single crystal were observed at 2.37 eV, 2.18 eV, and 1.81 eV. In the single crystal, the donor level of 0.25 eV, the acceptor levels of 0.97 eV and 0.41 eV were obtained by TSC, PICTS, and absorption measurements. The photoluminescence peaks were analyzed to relate to the indirect conduction band, the donor level, and the acceptor levels.

• 전기전자학회논문지
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• 제25권1호
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• pp.15-24
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• 2021

본 논문에서는 CDT(Conventional Double Trench) MOSFET보다 스위칭 시간과 손실이 적은 1700 V EPDT(Extended P+ shielding floating gate Double Trench) MOSFET 구조를 제안하였다. 제안한 EPDT MOSFET 구조는 CDT MOSFET에서 소스 Trench의 P+ shielding 영역을 늘리고 게이트를 N+와 플로팅 P- 폴리실리콘 게이트로 나누었다. Sentaurus TCAD 시뮬레이션을 통해 두 구조를 비교한 결과 온 저항은 거의 차이가 없었으나 Crss(게이트-드레인 간 커패시턴스)는 게이트에 0 V 인가 시에는 CDT MOSFET 대비 32.54 % 줄었고 7 V 인가 시에는 65.5 % 감소하였다. 결과적으로 스위칭 시간 및 손실은 각각 45 %, 32.6 % 줄어 스위칭 특성이 크게 개선되었다.

• Carbon letters
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• 제6권4호
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• pp.227-233
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• 2005

Carbonization products C1, C2, C3, C4 and C5 were prepared by the carbonization of date pit in limited air, at 500, 600, 700, 800 and $1000^{\circ}C$, respectively. C1-V-600, C3-V-600, C1-V-1000 and C3-V-1000 were prepared by thermal treatment of C1 and C3 under vacuum at 600 and $1000^{\circ}C$. The textural properties were determined from nitrogen adsorption at 77 K and from carbon dioxide adsorption at 298 K. The surface pH, the FTIR spectra and the acid and base neutralization capacities of some carbons were investigated. The amounts of surface oxygen were determined by out-gassing the carbon-oxygen groups on the surface as $CO_2$ and CO. The adsorption of water vapor at 308 K on C1, C2, C3 and C4 was measured and the decomposition of $H_2O_2$ at 308 K was also investigated on C1, C2, C3, C4 and C5. The surface area and the total pore volume decreased with the rise of the carbonization temperature from 500 to $1000^{\circ}C$. The adsorption of water vapor is independent on the textural properties, while it is related to the amount of acidic carbon-oxygen groups on the surface. The catalytic activity of $H_2O_2$ decomposition does not depend on the textural properties, but directly related to the amount of basic carbon-oxygen complexes out-gassed as CO, at high temperatures.