• The KIPS Transactions:PartB
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• v.9B no.1
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• pp.105-112
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• 2002

In order to process video data effectively, we need to save its content on database and a content-based retrieval method which processes various queries of all users is required. In this paper, we present VRS(Video Retrieval System) which provides similarity query, SQBE(Scene Query By Example) query, and content-based retrieval by combining the feature-based retrieval and the annotation-based retrieval. The SQBE query makes it possible for a user to retrieve scones more exactly by inserting and deleting objects based on a retrieved scene. We proposed query language and query processing algorithm for SQBE query, and carried out performance evaluation on similarity retrieval. The proposed system is implemented with Visual C++ and Oracle.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.6
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• The KIPS Transactions:PartD
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• v.14D no.6
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• pp.605-614
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• 2007

As a standard query language to search XML data, XQuery and XPath were proposed by W3C. By widely using XQuery and XPath languages, recent researches focus on the development of query processing algorithm and data structure for efficiently processing XML query with the enormous XML database system. Recently, when processing XML path expressions, the concept of the structural join which may determine the structural relationship between XML elements, e.g., ancestor-descendant or parent-child, has been one of the dominant XPath processing mechanisms. However, structural joins which frequently occur in XPath query processing require high cost. In this paper, we propose a new structural join algorithm, called SISJ, based on our structured index, called SI, in order to process XPath queries efficiently. Experimental results show that our algorithm performs marginally better than previous ones. However, in the case of high recursive documents, it performed more than 30% by the pruning feature of the proposed method.

• The Journal of Society for e-Business Studies
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• v.9 no.3
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• pp.259-276
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• 2004

ebXML and Web Services provide UDDI and ebXML registry for storing and managing the business and Service information of companies, respectively. Recently, W3C have released the OWL(Web Ontology Language) to Recommendation, and OWL-S proposed to describe the semantics of Web Services using the OWL ontologies. In this paper, we compared the OWL-S with the registry information model(RIM) of ebXML and the data structure of UDDI, and directly connect ones, which that of ebXML similar to that of UDDI; we extend the structure of the OWL to connect the rests. Consequently, our system enables to construct the ontologies of services and discover their semantics by using the information stored in the registries, and tintegrate UDDI, ebXML registry and OWL-S registry. By using the extending OWL-S documents in our system, agents can utilize for the semantic matchmaking.

• The Journal of Korean Association of Computer Education
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• v.16 no.4
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• pp.33-45
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• 2013

This paper aims at exploring how a high school student is engaged with C computer programming language and explore deep aspects of programming experiences based on video recalled interview as part of portraiture. The single case was selected and several in-depth interviews and video recording were arranged after Oct 2011. The portrait of K reveals interesting strands of his computer programming experiences with his own thinking patterns and exploring ideas for more concrete ways of coding his thinking similar to scientific experiments; ie, design-development-implementation-debugging-revision. Overall, this case illustrates how the inner aspects of subjective programming experiences on the tower of Hanoi were integrated and unified within himself for inner growth. We discussed the student's inner faculties as part of the student's unity and suggested future research direction.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.37 no.3
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• pp.45-55
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• 2000

In this paper, we proposed the hardware architecture of wavelet transform digital filter for an image processing. Filter bank pyramid algorithm is used for wavelet transform and each fillet is implemented by the FIR filter. For DWT computation, because the memory controller is implemented by hardware, we can efficiently process the multisolution decomposition of the image data only input the parameter. As a result of the image Processing in this paper, 33㏈ PSNR has been obtained on 512$\times$512 B/W image due to 11-bit mantissa processing in FPGA Implementation. And because of using QMF( Quadrature Mirror Filter) properties, it reduces half number of the multiplier needed DWT(Discrete Wavelet Transform) computation so the hardware size is reduced largely. The proposed scheme can increase the efficiency of an image Processing as well as hardware size reduced. The hardware design proposed of DWT fillet bank is synthesized by VHDL coding and then the test board is manufactured, the operating Program and the application Program are implemented using MFC++ and C++ language each other.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.781-788
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• 2017

This paper proposes a new algorithm for comparing amplitude between multiple digital input signals and its digital logic architecture. After simultaneously comparing multiple inputs, the proposed algorithm can provide the information of the largest (or smallest) value among them by using a simple digital logic function. The drawback of the method is to increase hardware resource. To overcome this we propose a reuse method of the overlapped logic operation. The proposed method focuses on enhancing the operational clock frequency, in other words decreasing combinational delay time. After implementing the comparing method with HDL (hardware description language), we experiment on it with environment of Cyclone III EP3C40F324A7 FPGA of Altera Inc. In case of 4 input signals, it can increase the operational speed as mush as 1.66 times with 1.20 times the hardware resource. In case of 8, it can also have 2.29 times the clock frequency and 2.15 times the hardware resource.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1346-1353
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• 1996

In this paper, we propose a modeling method for the flip-flops and test generation algorithms to detect the faults in the sequential circuits using VHDL in the high-level design environment. RS, JK, D and T flip-flops are modeled using data flow types. The sequence of micro-operation which is the basic structure of a chip-level leads to a control point where varnishing occurs to one of two micro- operation sequence. In order to model the fault of one micro-operation(FMOP) that perturb another micro-operation effectively, the concept of goal trees and some heuristic rules are used. Given a faulty FMOP or fault of control point (FCON), a test pattern is generated by fault sensitization, path sensitization and determination of the imput combinations that will justify the path sensitization. The fault models are restricted to the data flow model in the ARCHITECTURE statement of VHDL. The proposed algorithm is implemented in the C language and its efficiency is confirmed by some examples.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1240-1252
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• 1996

In this paper we propose a layout editor for the functional module generation in the Sea-of Gates(SOG) lay-out style. The proposed layout editor provides interactive was of designing a functional module to the designer so that the layout result is very satisfiable. Especially, the editor is independent on the shape of the basic cells in the gate array template, and provides semi-automatic layout methods as well as hand layout. It also has several special functions which are not able to find in other layout tools for the module generation, and hence the designer can generate modules very fast. The layout editors implemented in C language with X-win-dow Motif environment. When we compare our editor with the previous layout editor Seadali, the design time is reduced by a factor of two for several benchmark circuits.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2421-2429
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• 2000

With the advance of wireless communications technology, mobile communications have become more convenient than ever. Nowadays, people can communicate with each other on any place at any time. However, because of the openness of wireless communications, the way to protect the privacy between communicating parties is becoming a very important issue. In this paper, we present a study on the authentication and message encryption algorithm to support roaming service to the GSM network. To propose an authentication and message encryption algorithm applicable to the GSM system, the security architecture of the GSM outlined in the GSM standard is briefly introduced. In the proposed cryptosystems we use a new hash function for user authentication and a stream cipher based on Linear Feedback Shift Register(LFSR) for message encryption and decryption. Moreover, each algorithm is programmed with C language and simulated on IBM-PC system and we analyze the randomness properties of the proposed algorithms by using statistical tests.