• Proceedings of the Korean Association of Geographic Inforamtion Studies Conference
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• 2010.09a
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• pp.326-329
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• 2010

현재 시행 중인 승용차 RFID 요일제는 제한적인 설치장소와 RFID 설치시 많은 비용이 소비된다. 따라서 본 연구에서는 기존의 RFID 승용차 요일제 방식과 달리 효율성을 높이고 비용을 절감할수 있는 BMS(BUS Management System)를 활용한 버스 RFID system에 관한 방안을 제안한다. 제안하는 방안은 버스 RFID system은 대구시의 시내 버스 뒤편에 양쪽 상단에 RFID 안테나를 설치하여 대구시의 주요 도로를 운행 하며 승용차 요일제를 미준수 여부를 파악하는 것이다. 기존의 고정형 RFID는 설치 위치를 우회 할수 있지만 버스 RFID는 항상 이동하며 감지 하기때문에 차량의 우회에 따른 미확인 경우를 줄일 수 있다. 또한, BMS 활용으로 설치비용을 절감하여 비용대비 효율성을 제고할 수 있을 것으로 예상된다. 구체적인 방안 마련을 위하여 주요도로 버스노선도 파악, 중첩지점 그리고 기존의 승용차 요일제 시스템과 비교 분석을 하여 성능 평가들 실시하는 것에 주안점을 두고 연구를 수행하였다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.1
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• pp.113-120
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• 2015

Network type distributed control system uses a communication line which is named the BUS to exchange a data among the sub-systems. Usually, on the bus, only one data must be exited at one time, so the control algorithm to prevent collision or to manage a priority of data is important. Including CAN Protocol, many kind of FieldBus which are used for distributed control system, prevent data collision by controlling transmission time. But, a system which have to make a control signal or get a data from a sensor at fixed time will be met a problem when it is composed by using a network type distributed control structure. In this paper, some of these cases will be discussed and solutions be proposed for preventing a data collision. Also, using Arago Disk System which have a structure for inner loop control, the validity of the proposed methods will be verified.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.406-410
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• 1991

This paper presents an improved algorithm of optimal measurement system design with a reliability evaluation method for large power system. The proposed algorithm is developed to consider the dummy bus and to achieve highest accuracy of the state estimator as well with the limited Investment cost. The dummy bus in the power system is impossible to install measurement meter, while real and reactive power measurement values are exactly zero. Thus, the effect on these dummy bus measurements is considered in the proposed algorithm. On the other hand, P/C model is developed by taking advantage of the matrix sparsity. The improved program is successfully tested for KEPCO system with PSS/E lineflow calculated data package.

• 전기의세계
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• v.23 no.1
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• pp.61-68
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• 1974

This paper attempts to develop the algorithms and computer program for load flow solution and faults analysis of large power system by small digital computer. The Conventional methods for load flow solution and fault analysis of large power system require too much amount of computer memory space and computing time. Therefore, this paper describes the methad for reducing the computer memory space and computing time as follows. (1) Load Flow Solution; This method is to store each primitive impedance of lines along with a list of bus numbers corresponding to the both terminals of lines, and to store only nonzero element of bus admittance matrix. (2) Faults Analysis: This method is to partition a large power system into several groups of subsystems, form individual bus impedance matrix, store them in the storage, and assemble the only required portion of them to original total system by algorithm.

• Proceedings of the KIEE Conference
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• 2004.07e
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• pp.27-29
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• 2004

This paper presents improved teaching and learning Gill for easily analysis tool of load flow of power system. This GUI includes not only contingency analysis function, but also calculating power loss from transmission line flow. The Gill is friendly for study for power system operation and control because picture provide a better visualizing of relationships between input parameters and effect than a tabula type result. This Gill enables topology and the output data of load flow for line outages to be shown on same picture page. Users can input the system data for power flow on the the picture and can easily see the the result diagram of bus voltage, bus power, line flow. It is also observe the effects of different types of variation of tap, shunt capacitor, loads level, line outages. Proposed Gill has been studied on the Ward-Hale 6-Bus system.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.2
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• pp.133-141
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• 1990

In the operation of an electric power system, the voltage security of the system has acquired more significant importance after the occurrence of large system black-outs caused by voltage collapse several times. This paper describes a fast contingency screening method concerning voltage security. The method defines a voltage-sensitive buses where significant voltage changes would occur as a result of the contingency to reduce the number of bus voltages to be solved for continngency screening. This method is based on the observation that it is not necessary to solve the entire network in most contingency cases because boltage changes actually occur around the contingency. The P-Q decoupled linearized model and the fast error correction method are also adopted in the method to define voltage-sensitive buses and to calculate voltage magnitude on the selected voltage-sensitive buses fastly and reliably. The method suggested in this papaer has been tested in IEEE 30-bus model system and KEPCO 130-bus actual system and its effectiveness for practical use has also been confirmed.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.11
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• pp.637-642
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• 2000

IEEE 1149.1 boundary scan architecture is used as a standard in board-level system testing. The simplicity of this architecture is an advantage in system testing, but at the same time, it it makes a limitation of applications. Because of several problems such as 3-state net conflicts, or ambiguity issues, interconnect testing for multi-drop multi-board systems is more difficult than that of single board systems. A new approach using IEEE 1149.1 boundary scan architecture for multi-drop multi-board systems is developed in this paper. Adding boundary scan cells on backplane bus lines, each board has a complete scan-chain for interconnect test. This new scan-path insertion method on backplane bus using limited 1149.1 test bus less area overhead and mord efficient than previous approaches.

• International Journal of Fluid Machinery and Systems
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• v.8 no.1
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• pp.13-22
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• 2015

This study presents a simulation model of a heat pump air conditioning system with a variable capacity compressor and variable speeds fans for electric bus. An experimental sample has been developed in order to check results from the model. Effects on system performance of such working conditions as compressor speed, evaporator fans speeds and the condenser fans speeds have been simulated by means of developed model. The results show that the three speeds can be adjusted simultaneously according to actual working condition so that the AC system can operate under the optimum state which the control objects want to achieve. It would be a good and simple solution to extend the driving ranges of EVs because of the highest efficiency and the lowest energy consumption of AC system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2078-2082
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• 2010

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. Conventional arbitration method is considered bus priority primarily, actual bus utilization didn't considered. In this paper, we propose arbitration method using bus utilization operating block of each master, we verify the performance compared with the other arbitration methods through throughput performance. From the result of performance verification, we confirm that proposed arbitration method, matched bus utilization set by the user 40%, 20%, 20%, 20%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.885-888
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• 2015

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.