• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.94-101
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• 2010

Optimization of interconnects among processors and memories becomes important as multiple processors and memories can be integrated on a Multi-Processor System-on-Chip (MPSoC). Since the optimal interconnection architecture is usually dependent on the applications, systematic design methodology for various data transfer requirements is necessary. In this paper, we focus on bus interconnection for MPSoC applications which use 4 ~ 16 processors. We propose a new systematic bus design methodology under performance constraints using Single Arbitration Multiple Bus Accesses (SAMBA) style bus architectures. Optimized bus architecture is found to satisfy performance constraints for a single or multiple applications. When compared to the unoptimized architecture, our method can reduce the bus switch logic circuits significantly (by more than 50% sometimes). Furthermore, low cost bus architectures can be found to satisfy the performance constraints for multiple applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.12B
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• pp.1548-1555
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• 2011

In ultra-deep submicron technology, minimization of propagation delay and power consumption on buses is one of the most important design objectives in system-on-chip (SOC) design. Crosstalk between adjacent wires on the bus may create a significant portion of propagation delay. Elimination or minimization of such faults is crucial to the performance and reliability of SOC designs. Most of the previous works on bus encoding are targeted either to minimize the bus switching or minimize the crosstalk delay, but not both. This paper proposes a new bus encoding scheme which can adaptively select one of functions "invert" and "logic-convert" according the number of bus switching on an encoded 4-bit cluster. This scheme leads to minimization of both crosstalk and bus switching. In experiment result, our proposed encoding technique consumes about 25% less power over the previous, while completely eliminating the crosstalk delay.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.343-350
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• 2016

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connects (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 39K at an operating frequency of 313MHz using the $0.13{\mu}m$ TSMC process.

• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.249-250
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• 2011

In DC Power Distribution System(DC PDS), a bus voltage instability is occurred by multiple parallel loads. The Voltage Bus Conditioner(VBC) is used to mitigate the DC bus voltage transient. An adaptive controller of the VBC is designed and the simulation result of the controller is verified by PSIM simulation package for the proposed control technique.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1141-1142
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• 2011

An electrical vehicle (EV) is a huge issue in the automotive industry. The EV have many electrical units: electric motors, batteries, converters, ets. The DC power distribution system (PDS) is essential for the EV. The DC PDS offers many advantages. However, multiple loads in the DC PDS may affect the severe instability on the DC bus voltage. Therefore, a voltage bus conditioner (VBC) may use the DC PDS. The VBC is used to mitigate the voltage transient on the bus. In this paper, sliding mode controller (SMC) is designed for the VBC of DC PDS in the EV. The simulation results by PISM simulation package are presented for validating the proposed control technique.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.12
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• pp.2195-2201
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• 2010

The VBC(Voltage Bus Conditioner) is a bidirectional DC-DC converter with the energy storage for damping the instability and any transients of bus voltage in the DC DPS(Distributed Power System). This paper presents the PI(Proportional Integration) controller for the VBC. The PI controller is not only damping the bus transient, but also keeping the storage voltage level. Matlab Simulink simulation and experimental results are presented by validity of the proposed control technique.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.56 no.2
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• pp.90-98
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• 2007

More and All-Electric Aircraft (AEA) carry many loads with varied functions. In particular, there may be large pulsed loads with short duty ratio, which can affect the normal operation of other loads. In this paper, a bi-directional converter with inductive storage is used as a voltage bus conditioner (VBC) to mitigate voltage transients on the bus. In addition, the constant frequency hysteresis control technique for a VBC is presented. A simple and fast prediction of the hysteresis band-width is implemented by the phase-lock loop control, keeping constant switching frequency. This technique offers the excellent dynamic response in load or parameter variation. The control performance is illustrated by simulated results with the SABER package, The proposed hysteresis control results in the shortest and the smallest excursions.

• Proceedings of the Safety Management and Science Conference
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• 2000.05a
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• pp.97-110
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• 2000

Production schedule and realization quantity of Large type bus [929(HD), 928, 928-A(SD), 937E/L, 937/L,] were analyzed in order to intruoduce FMS(Flexible Manufacturing System) appropriate for varities of customer desire and multi-item, small lot production. And this paper is aimed to propose introduction method of FMS, analyzing zig tools change times and idle times with production line and workers as an object. According to analysis results, only simple spec., depending on bus type, changed with decrease in production. For 929(HD), 928,928-A(SD), 937Eh, 937/L bus type, there was no harmony between schdule and realization. Therefore, it caused many difficulties in part supply. And there was loss of manpower and reduction of productibility due to idle time of process with bus type change. Production processes were operated inefficiently because tact time exceeded or shortaged of allow time.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1098-1100
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• 2005

The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. And then, as the DSM advances, the VLSI chip becomes more congested even though more metal layers are used for routing. Usually, a VLSI chip includes several buses. As design increases in complexity, bus routing becomes a heavy task. To ease bus routing and avoid unnecessary iterations in physical design, we need to consider bus planning in early floorplanning stage. In this paper, we propose a floorplanning method for topological constraint consisting of bus constraint and memory constraint. The proposed algorithms based on Genetic Algorithm(GA) is adopted a sequence pair. For selection control, new objective functions are introduced for topological constraint. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA in consideration of topological constraint. Experimental results show improvement of bus and memory constraint.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.76-91
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• 1996

In this paper, we proposed the new medium access control protocol for the virtual token bus netowrk. The network is applied to inter-processor communication network of large capacity digital switching system and digital mobile system with distributed control architecture. in the virtual token bus netowrk, the existing medium access control protocols hav ea switchove rtime overhead when traffic load is light or asymmetric according ot arbitration address of node that has message to send. The proposed protocol optimized average message delay using cyclic bus access chain to exclude switchover time of node that do not have message to send. Therefore it enhanced bus tuilization and average message delay that degrades the performance of real time communication netowrks. It showed that the proposed protocol is more enhacned than virtual token medium access control protocol and virtual token medium access control protocol iwth reservation through performance analysis.