• Title/Summary/Keyword: Bus System

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A Basic Study on Analysis of Influencing factor of Bus Accidents in Bus Lane Section (버스전용차로 구간 유형별 버스사고영향요인 분석 기초연구)

  • Park, Jun-Tae;Kim, Hyun-Jin;Kim, Jung-Yeol;Jang, Il-Jun;Lim, Joon-Bum
    • Journal of the Korean Society of Safety
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    • v.27 no.3
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    • pp.153-160
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    • 2012
  • Various social problems such as traffic congestion, car accidents and environmental problems(air pollution, noises etc.) have been happening in the Seoul metropolitan area that has the car oriented traffic system providing cars continuously. Along with this, the financial burden caused by current oil price anxiety made paradigm shift from caroriented to public transportation-oriented. Its typical example is an arterial branch bus system changing(bus lane through the center of main road) started in Seoul in July, 2004. But study on safety analysis of bus lane and characteristic of accidents are not sufficient enough to now. The bus lanes are expanded to provide roads for better traffic operation and accidents between buses and pedestrians or ordinary vehicles are considered main problems. This study divided each bus route of median bus lane(bus-only lane through the center of main roads) and bus lane at roadside by intersection and collected and analysed data about influence variables of bus accidents chosen in each section. We constructed a logistic model using collected data. As a result, bus lane at roadside are used by both buses and other kinds of vehicles differently from median bus lane and showed such characteristic in accident influence. Therefore access management to factors causing conflict and improvement of operation management are required. In case of median bus lane, the more buses moving general vehicle lane and traffic volume of section were, the more accidents happened. In case that stop line of center lane is not backward, view blocking of vehicles turning left caused accidents.

System Dynamics Interpretation on Bus Scheduling Model (시스템 다이나믹스 관점에서의 버스 운영계획모형 해석)

  • Kim, Kyeong-Sik
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.8 no.1
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    • pp.1-8
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    • 2009
  • This paper aims mainly to reinterpretate Optimal Bus Scheduling Model by applying System Dynamics Perspective. Traditionally, the study regarding Optimal Bus Scheduling Model stems on the linear relationshp. However, this paper attempted to convert linear relationship based Optimal Bus Scheduling Model to causal loop perspective based Model. In result, the paper present Casual Loop Diagram for Optimal Bus Scheduling Model. Furthermore, the paper also ran a simulation based on Stock & Flow Diagram for Optimal Bus Scheduling Model. The outcome was not much different from the linear relationship based Model due to the similarity of the equation applied on two models.

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Study on Side Impact Test Procedure of Hydrogen Bus (수소버스 측면충돌 시험방법 연구)

  • Kim, Kyungjin;Shin, Jaeho;Han, Kyeonghee;In, Jeong Min;Shim, Sojung;Kim, Siwoo
    • Journal of Auto-vehicle Safety Association
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    • v.13 no.4
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    • pp.92-98
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    • 2021
  • Recently hydrogen fuel cell buses have been deployed for the public transportations. In order to introduce buses fueled by hydrogen successfully, the research results of hydrogen bus safety should be discussed and investigated significantly. Especially, Korean government drives research in terms of various applications of hydrogen energy to replace the conventional fuel energy resources and to improve the safety evaluation. Thus it is necessary to examine vehicle crashworthiness under side impact loadings. This study was focused on the simulation result evaluation of full bus model and simplified bus model with hydrogen fuel tank module and mounting system located below floor structure due to the significance of bus side impact accidents. The finite element models of hydrogen bus, fuel tank system and side impact moving barrier were set up and simulation results reported model performance and result comparison of two side impact models. Computational results and research discussion showed the conceptual side impact framework to evaluate hydrogen bus crashworthiness.

Design of Safety School Bus System Using RFID (RFID를 활용한 안전 스쿨버스 시스템 설계)

  • Kim, Ji-Yeon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.11
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    • pp.1741-1746
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    • 2022
  • As the use of school buses becomes more common, related laws are being enacted, such as making it mandatory for children to check school bus dropouts due to frequent accidents caused by the negligence of school bus drivers and their guardians. In this paper, we propose a safe school bus system that links efficient radio-frequency identification (RFID) and mobile APP in terms of energy utilization and cost. The school bus system uses RFID cards to check information on children boarding the school bus, and real-time SMS transmission allows parents to safely send their children to and from school. Instructors on the school bus can check their children's disembarkation information once more through APP, preventing various accidents that may occur to children left on the bus. Due to the automation of the school bus operation log, daycare center teachers can not only check the information on getting on and off, but also manage the information on the attendance and discharge of the students.

Modeling & Analysis of the System Bus on the SoC Platform (SoC 플랫폼에서 시스템 버스의 모델링 및 해석)

  • Cho Young-shin;Lee Je-hoon;Cho Kyoung-rok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.12
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    • pp.35-44
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    • 2005
  • SoC(systnn-on-a-chip) requires high bandwidth system bus for performing multiple functions. Performance of the system is affected by bandwidth of the system bus. In this paper, for efficient management of the bus resource on a SoC platform, we present a latency model of the shared bus organized by multiple layers. Using the latency model, we can analyze latencies of the shared bus on a SoC. Moreover we evaluate a throughput of the bus and compare with needed throughput of the SoC platform including IPs such as MPEG or USB 2.0. And we can use the results as a criteria to find out an optimal bus architecture for the specific SoC design. For verifying accuracy of the proposed model, we compared the latencies with the simulation result from MaxSim tools. As the result of simulation, the accuracy of the IS model for a single layer and multiple layer are over $96\%\;and\;85\%$ respectively.

Study on Safety Evaluation Process for Hydrogen Storage System of Hydrogen Bus (수소버스 수소저장용기의 측면충돌 안전성 평가방법 연구)

  • Kyungjin, Kim;Jaeho, Shin;Kyeonghee, Han;Hyeon Min, Han;Jeong Min, In;Siwoo, Kim
    • Journal of Auto-vehicle Safety Association
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    • v.14 no.4
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    • pp.113-119
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    • 2022
  • The structural safety of hydrogen buses is being evaluated for the successful introduction of hydrogen buses. The crash test methodology, for example, side impact test procedure is being discussed for hydrogen bus structure safety with a compressed hydrogen storage system located under the bus floor. Thus this study describes a new experiment method for side impact test with compressed hydrogen storage system independently based on finite element analysis instead of side impact test using full hydrogen bus. A side crash procedure of conceptual compressed hydrogen storage structure was investigated and impact simulations were performed. The finite element models of hydrogen bus, simplified structures, fuel tank system and side impact moving barrier were set up and simulation results reported model performance and result comparison of three different simplified models. Computational results and research discussion proposed the fundamental test framework for safety assessment of the compressed hydrogen storage system.

A Novel Globally Asynchronous, Locally Dynamic System Bus Architecture Based on Multitasking Bus (다중처리가 가능한 새로운 Globally Asynchronous, Locally Dynamic System 버스 구조)

  • Choi, Chang-Won;Shin, Hyeon-Chul;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.5
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    • pp.71-81
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    • 2008
  • In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

Partial Bus-Invert Coding for System Level Power Optimization (부분 버스 반전 부호화를 이용한 시스템 수준 전력 최적화)

  • 신영수;채수익;최기영
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.12
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    • pp.23-30
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    • 1998
  • We present a partial bus-invert coding scheme for system-level power optimization. In the proposed scheme, we select a sub-group of bus lines involved in bus encoding to avoid unnecessary inversion of bus lines not in the sub-group thereby reducing the total number of bus transitions. We propose a heuristic algorithm that selects the sub-group of bus lines for bus encoding. Experiments on benchmark examples indicate that the partial bus-invert coding reduces the total bus transitions by 62.6% on the average, compared to that of the unencoded patterns. We also compare the performance of the proposed heuristic algorithm with that of simulated annealing, which shows that it is highly efficient.

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Investigating the Monetary Value of Bus Arrival Time Information (실시간 버스도착정보의 가치 측정에 관한 연구)

  • Bin, Mi-Young;Kim, Hyo-Bin
    • Journal of Korean Society of Transportation
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    • v.23 no.6 s.84
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    • pp.81-89
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    • 2005
  • Real-time bus arrival information within the Bus Information System (BIS) is an invaluable resource for users that demand accurate and up-to-date bus headway information while waiting at a bus stop. The associated benefits of such a system come in two folds, that is to 1) resolve the psychological uncertainty caused by the lack of real-time bus arrival information and 2) empower the user waiting at bus stops with the ability to reliably coordinate various tasks and errands, such as a quick trip into a convenience store or restroom without fear of missing a bus pick-up. This paper discusses the appropriate methodology with which to measure the economic value of reliable bus arrival information, with particular emphasis on the psychological uncertainty in users associated with the lack of real-time headway information at bus stops. Data regarding bus transit users' willingness to pay for such a service is obtained through questionnaire surveys, and the Contingent Valuation Method is used to analyze and derive the associated economic value. Our findings indicate the monetary value associated with a real-time bus arrival information system is approximately 132.5 won/min at the 0.3 significance level.

An Improvement of Implementation Method for Multi-Layer AHB BusMatrix (ML-AHB 버스 매트릭스 구현 방법의 개선)

  • Hwang Soo-Yun;Jhang Kyoung-Sun
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.11_12
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    • pp.629-638
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    • 2005
  • In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.