• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.99-107
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• 2013

Controller area network (CAN) was designed for multiplexing communication between electronic control units (ECUs) in vehicles and thus for decreasing the overall wire harness. The increasing number of ECUs causes the CAN bus overloaded and consequently the error probability of data transmission increases. Since the time duration for the data transmission is proportional to CAN frame length, it is desirable to reduce the frame length. In this paper, a CAN message compression method is proposed using Data Length Code (DLC) and compression area selection algorithm to reduce the CAN frame length and the error probability during the transmission of CAN messages. By the proposed method, it is not needed to predict the maximum value of the difference in successive CAN messages as opposed to other compression methods. Also, by the use of DLC, we can determine whether the received CAN message has been compressed or not without using two ID's as in conventional methods. By simulations using actual CAN data, it is shown that the CAN transmission data is reduced up to 52 % by the proposed method, compared with conventional methods. By using an embedded test board, it is shown that 64bit EMS CAN data compression can be performed within 0.16ms and consequently the proposed algorithm can be used in automobile applications without any problem.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• KIPS Transactions on Computer and Communication Systems
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• v.6 no.3
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• pp.105-112
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• 2017

PCI Express is a bus technology that connects the processor and the peripheral I/O devices that widely used as an industry standard because it has the characteristics of high-speed, low power. In addition, PCI Express is system interconnect technology such as Ethernet and Infiniband used in high-performance computing and computer cluster. PGAS(partitioned global address space) programming model is often used to implement the one-sided RDMA(remote direct memory access) from multi-host systems, such as computer clusters. In this paper, we design and implement a OpenSHMEM API based on PCI Express maintaining the existing features of OpenSHMEM to implement RDMA based on PCI Express. We perform experiment with implemented OpenSHMEM API through a matrix multiplication example from system which PCs connected with NTB(non-transparent bridge) technology of PCI Express. The PCI Express interconnection network is currently very expensive and is not yet widely available to the general public. Nevertheless, we actually implemented and evaluated a PCI Express based interconnection network on the RDK evaluation board. In addition, we have implemented the OpenSHMEM software stack, which is of great interest recently.

• Journal of Preventive Medicine and Public Health
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• v.27 no.3 s.47
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• pp.475-486
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• 1994

In order to provide necessary information for better health of workers through understanding the actual status of the industries adopting shift systems. The data were gathered from a stratified random sample of 347 (0.5%) firms selected out of about 70,000 manufacturing industries throughout the nation in 1993. Stratification during sampling was by industrial group and number of workers. The major findings obtained from 288 firms surveyed completely were as follows : 1. About 20.2% of the 288 firms were adopting shift systems and shirtworkers accounted for about 25.1% of the total work force in 288 firms. 2. The bigger number of workers was, the higher the adopting rate of shift system was. 3. The rate of having welfare facilities such as dining room, commuting bus, washing facilities, and health care room etc. was higher in the industries adopting shift systems. 4. The major industrial groups adopting shift systems were the rubber a: plastic goods manufacturing industry (54.1 per 100 firms) and the textile manufacturing industry (44.8 per 100 firms). However, the proportion of shiftworkers was higher in the textile manufacturing industry (70.5 per 100 firms) and the electronics industry (57.9 per 100 frms). 5. The most predominant work schedule was the weekly rotating, semi-continuos 2-crew 2-shift system (47.5%). 6. In the industries adopting shift systems, shiftworkers had an adjusted average of 0.29 spells per 100 workers ($0.14{\sim}0.45$ in 95% C.I.) compared to 0.23 spells per 100 nonshift dayworkers ($0.15{\sim}0.31$ in 95% C.I.) for 1 month. 7. Also, in the industries adopting shift systems, the adjusted average annuel turn-over rate of shiftworkers was 13.07 per 100 workers ($12.03{\sim}14.12$ in 95% C.I.) compared to 10.18 per 100 nonshift dayworkers ($9.53{\sim}10.82$ in 95% C.I.).

• Journal of Astronomy and Space Sciences
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• v.21 no.4
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• pp.399-416
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• 2004

The FIMS (Far-ultraviolet IMaging Spectrograph), the main payload onboard the first Korean science satellite STSAT-1, has performed various observations since its launch on September 2003. It has been found that the attitude informations provided by spacecraft bus system have a time offset problem, and the problem has been extensively studied. After the time offset correction, boresight offsets between FIMS fields of view, of long and short wavelength bands, respectivley, and spacecraft attitude systems, which are mainly due to alignment error between the FIMS and spacecraft mechanical systems, were calculated through the observations of well known calibration targets. Monthly status and precision of the attitude information are also described. Correction methods for spatially variable exposure, intrinsic to FIMS data, are discussed. These results are essential to the FIMS data analysis, and will be used as references for subsequent studies on more accurate attitude corrections.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.557-565
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• 2005

This paper presents the development and implementation of a zero-copy file transfer mechanism that improves the efficiency of file transfers for PC cluster systems using hardware-based VIA(Virtual Interface Architecture) network adapters. VIA is one of the representative user-level communication interfaces, but because there is no library for file transfer, one copy occurs between kernel buffer and user boilers. Our mechanism presents a file transfer primitive that does not require the file system to be modified and allows the NIC to transfer data from the kernel buffer to the remote node directly without copying. To do this, we have developed a hardware-based VIA network adapter, which supports the PCI 64bit/66MHz bus and Gigabit Ethernet, as a NIC, and implemented a zero-copy file transfer mechanism. The experimental results show that the overhead of data coy and context switching in the sender is greatly reduced and the CPU utilization of the sender is reduced to $30\%\~40\%$ of the VIA send/receive mechanism. We demonstrate the performance of the zero-copy file transfer mechanism experimentally. and compare the results with those from existing file transfer mechanisms.

• Journal of Korean Society of Rural Planning
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• v.6 no.1 s.11
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• pp.19-28
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• 2000

Now in order to overcome the weakest points of the rural areas of the city of Kimje and, transform them into rural cultural villages which have local governing systems suitable to new localization age and activate this plan, we selected Daesan Village as a model village which had shown a lot of potentials in the basic research and studied it dividing it into the former part and the latter part. We studied Daesan village in the former part focusing on state analysis and basic ideas and in the latter part focusing on master plan and detail planning. We can summarize the conclusion like the followings. 1. Daesan Village located 8 kilometer away from the downtown Kimje and the city of Iksan respectably has comparatively good environment of good sunny place as an open field whose surrounding configuration of the ground consists of farming lands and low hills in front and rear. It has 38 farming households in all. 2. Human environment(인문환경); the village road whose width is about 4 meters is forming a flow system forking off into three. There is a route bus which operates three times a day even into the inside of the village. The main sources of revenue are vegetables in facilities, fruits and floriculture. Their average revenue is about 10.5 million won. 3. Here in DaeSan Village a legend dealing with Teasan literally meaning a big mountain consist of th village's tradition and you can see the tombs of a very faithful son and Anwi an army general in the age of the Japanese Invasion of Korea of 1592 to 1598 inside the village. 4. 85 out of the eitire population 141 whose age are over 20 showed very positive attitudes in a questionnaire about, making the village a cultural one and its development. 5. The basic of planned ideas is to increase the revenue of the farming household by making the village a professional farming one which has a state-of the-art production facility and agricultural technique. It is to make the village the one where people can enjoy the sense of the rural life and the farmer can enjoy their lives through consumptive and consistant leisure and resting activities. 6. We are planning to make entrance space, life space, rest and sport space, and cultural space considering the characteristics of the village and the demand of the resident. We are also planning to make tile entire city of Kimje an information transmitting base in short and long term perspectives. 7. DaeSan Village was planned as a place where tradition and the future exist together. On the basis of this concept we planned future programs for Daesan Village and in the latter part of the study master plans and detail plans will be continued.the regional agricultural condition. The development permissions were only during the period of restricted to use ($1979.12{\sim}1993.11$). We propose that the authority of development permission should be given to the local autonomy government, because the local government has the knowledge of its individual agricultural conditions.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of Internet Computing and Services
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• v.14 no.5
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• pp.69-76
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• 2013

The incidence of globally infectious and pathogenic diseases such as H1N1 (swine flu) and Avian Influenza (AI) has recently increased. An infectious disease is a pathogen-caused disease, which can be passed from the infected person to the susceptible host. Pathogens of infectious diseases, which are bacillus, spirochaeta, rickettsia, virus, fungus, and parasite, etc., cause various symptoms such as respiratory disease, gastrointestinal disease, liver disease, and acute febrile illness. They can be spread through various means such as food, water, insect, breathing and contact with other persons. Recently, most countries around the world use a mathematical model to predict and prepare for the spread of infectious diseases. In a modern society, however, infectious diseases are spread in a fast and complicated manner because of rapid development of transportation (both ground and underground). Therefore, we do not have enough time to predict the fast spreading and complicated infectious diseases. Therefore, new system, which can prevent the spread of infectious diseases by predicting its pathway, needs to be developed. In this study, to solve this kind of problem, an integrated monitoring system, which can track and predict the pathway of infectious diseases for its realtime monitoring and control, is developed. This system is implemented based on the conventional mathematical model called by 'Susceptible-Infectious-Recovered (SIR) Model.' The proposed model has characteristics that both inter- and intra-city modes of transportation to express interpersonal contact (i.e., migration flow) are considered. They include the means of transportation such as bus, train, car and airplane. Also, modified real data according to the geographical characteristics of Korea are employed to reflect realistic circumstances of possible disease spreading in Korea. We can predict where and when vaccination needs to be performed by parameters control in this model. The simulation includes several assumptions and scenarios. Using the data of Statistics Korea, five major cities, which are assumed to have the most population migration have been chosen; Seoul, Incheon (Incheon International Airport), Gangneung, Pyeongchang and Wonju. It was assumed that the cities were connected in one network, and infectious disease was spread through denoted transportation methods only. In terms of traffic volume, daily traffic volume was obtained from Korean Statistical Information Service (KOSIS). In addition, the population of each city was acquired from Statistics Korea. Moreover, data on H1N1 (swine flu) were provided by Korea Centers for Disease Control and Prevention, and air transport statistics were obtained from Aeronautical Information Portal System. As mentioned above, daily traffic volume, population statistics, H1N1 (swine flu) and air transport statistics data have been adjusted in consideration of the current conditions in Korea and several realistic assumptions and scenarios. Three scenarios (occurrence of H1N1 in Incheon International Airport, not-vaccinated in all cities and vaccinated in Seoul and Pyeongchang respectively) were simulated, and the number of days taken for the number of the infected to reach its peak and proportion of Infectious (I) were compared. According to the simulation, the number of days was the fastest in Seoul with 37 days and the slowest in Pyeongchang with 43 days when vaccination was not considered. In terms of the proportion of I, Seoul was the highest while Pyeongchang was the lowest. When they were vaccinated in Seoul, the number of days taken for the number of the infected to reach at its peak was the fastest in Seoul with 37 days and the slowest in Pyeongchang with 43 days. In terms of the proportion of I, Gangneung was the highest while Pyeongchang was the lowest. When they were vaccinated in Pyeongchang, the number of days was the fastest in Seoul with 37 days and the slowest in Pyeongchang with 43 days. In terms of the proportion of I, Gangneung was the highest while Pyeongchang was the lowest. Based on the results above, it has been confirmed that H1N1, upon the first occurrence, is proportionally spread by the traffic volume in each city. Because the infection pathway is different by the traffic volume in each city, therefore, it is possible to come up with a preventive measurement against infectious disease by tracking and predicting its pathway through the analysis of traffic volume.