• 제목/요약/키워드: Bus Electronic Unit

검색결과 40건 처리시간 0.025초

Centralized Adaptive Under Frequency Load Shedding Schemes for Smart Grid Using Synchronous Phase Measurement Unit

  • Yang, D.Y.;Cai, G.W.;Jiang, Y.T.;Liu, C.
    • Journal of Electrical Engineering and Technology
    • /
    • 제8권3호
    • /
    • pp.446-452
    • /
    • 2013
  • Under frequency load shedding (UFLS) is an effective way to prevent system blackout after a serious disturbance occurs in a power system. A novel centralized adaptive under frequency load shedding (AUFLS) scheme using the synchronous phase measurement unit (PMU) is proposed in this paper. Two main stages are consisted of in the developed technique. In the first stage, the active power deficit is estimated by using the simplest expression of the generator swing equation and static load model since the frequency, voltages and their rate of change can be obtained by means of measurements in real-time from various devices such as phase measurement units. In the second stage, the UFLS schemes are adapted to the estimated magnitude based on the presented model. The effectiveness of the proposed AUFLS scheme is investigated simulating different disturbance in IEEE 10-generator 39-bus New England test system.

MCU용 Fast 256Kb EEPROM 설계 (Design of a Fast 256Kb EEPROM for MCU)

  • 김용호;박헌;박무훈;하판봉;김영희
    • 한국정보통신학회논문지
    • /
    • 제19권3호
    • /
    • pp.567-574
    • /
    • 2015
  • 본 논문에서는 MCU(Micro Controller Unit) IC를 위한 50ns 256Kb EEPROM 회로를 설계하였다. 설계된 EEPROM IP는 기준전압을 이용한 차동증폭기 형태의 DB(Data Bus) 센싱 회로를 제안하여 읽기 동작시 데이터 센싱 속도를 빠르게 하였으며, DB를 8등분한 Distributed DB 구조를 적용하여 DB의 기생 커패시턴스 성분을 줄여 DB의 스위칭 속도를 높였다. 또한 기존의 RD 스위치 회로에서 5V 스위치 NMOS 트랜지스터를 제거함으로써 읽기 동작 시 BL의 프리차징 시간을 줄여 액세스 시간을 줄였고 데이터 센싱 시 DB 전압과 기준전압 간의 전압차 ${\Delta}V$를 0.2VDD 정도 확보하여 출력 데이터의 신뢰도를 높였다. 매그나칩반도체 $0.18{\mu}m$ EEPROM 공정으로 설계된 256Kb EEPROM IP의 액세스 시간은 45.8ns 이며 레이아웃 면적은 $1571.625{\mu}m{\times}798.540{\mu}m$이다.

상용차용 ABS의 ECU 설계 및 제어 알고리즘에 관한 연구 (A Study on the design of ABS ECU for a commercial vehicle(BUS) and its control algorithm)

  • 이기창;김문섭;전정우;황돈하;박도영;김용주
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2000년도 추계학술대회 논문집 학회본부 D
    • /
    • pp.612-614
    • /
    • 2000
  • ABS(Anti-lock Braking System) is a device which prevents the lock-up of car wheels during emergency braking. It helps to maintain the steerability since the tire-road slip is controlled in an acceptable range. By maintaining the maximal frictional force during braking. ABS can reduce the braking distance. Recently, ABS is accepted as a standard equipment in vehicles, especially in commercial vehicles(bus and trucks). Commercial vehicles mostly use pneumatic pressure for braking. In this paper, ECU(Electronic Control Unit) for the anti-lock braking system of a commercial vehicle which is equipped with a full-air brake system and its control algorithms are presented.

  • PDF

차량 내 네트워크 통신의 기능안전성을 위한 하드웨어 기본 설계 (Basic Design of ECU Hardware for the Functional Safety of In-Vehicle Network Communication)

  • 곽현철;안현식
    • 전기학회논문지
    • /
    • 제66권9호
    • /
    • pp.1373-1378
    • /
    • 2017
  • This paper presents a basic ECU(Electronic Control Unit) hardware development procedure for the functional safety of in-vehicle network systems. We consider complete hardware redundancy as a safety mechanism for in-vehicle communication network under the assumption of the wired network failure such as disconnection of a CAN bus. An ESC (Electronic Stability Control) system is selected as an item and the required ASIL(Automotive Safety Integrity Level) for this item is assigned by performing the HARA(Hazard Analysis and Risk Assessment). The basic hardware architecture of the ESC system is designed with a microcontroller, passive components, and communication transceivers. The required ASIL for ESC system is shown to be satisfied with the designed safety mechanism by calculation of hardware architecture metrics such as the SPFM(Single Point Fault Metric) and the LFM(Latent Fault Metric).

Low Power Trace Cache for Embedded Processor

  • Moon Je-Gil;Jeong Ha-Young;Lee Yong-Surk
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
    • /
    • pp.204-208
    • /
    • 2004
  • Embedded business will be expanded market more and more since customers seek more wearable and ubiquitous systems. Cellular telephones, PDAs, notebooks and portable multimedia devices could bring higher microprocessor revenues and more rewarding improvements in performance and functions. Increasing battery capacity is still creeping along the roadmap. Until a small practical fuel cell becomes available, microprocessor developers must come up with power-reduction methods. According to MPR 2003, the instruction and data caches of ARM920T processor consume $44\%$ of total processor power. The rest of it is split into the power consumptions of the integer core, memory management units, bus interface unit and other essential CPU circuitry. And the relationships among CPU, peripherals and caches may change in the future. The processor working on higher operating frequency will exact larger cache RAM and consume more energy. In this paper, we propose advanced low power trace cache which caches traces of the dynamic instruction stream, and reduces cache access times. And we evaluate the performance of the trace cache and estimate the power of the trace cache, which is compared with conventional cache.

  • PDF

하이브리드 연료전지 자동차의 CAN기반 실시간 시뮬레이터 구현 (Implementation of a CAN Based Real-Time Simulator for FCHEV)

  • 심성용;이남수;안현식;김도현
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
    • /
    • pp.410-413
    • /
    • 2004
  • In this paper, a simulator system for Fuel Cell Hybrid Electric Vehicles(FCHEV) is implemented using DSP boards with CAN bus. The subsystems of a FCHEV i.e., the fuel cell system, the battery system, the vehicle dynamics with the transmission mechanism are coded into 3 DSP boards. The power distribution control algorithm and battery SOC control are also coded into a DSP board. The real-time monitoring program is also developed to examine the control performance of power control and SOC control algorithms.

  • PDF

A Study on the ECU and Control Algorithm of ABS for a Commercial Vehicle

  • Lee, Ki-Chang;Kim, Mun-Sub;Jeon, Jeong-Woo;Hwang, Don-Ha;Park, Doh-Young;Kim, Yong-Joo
    • 제어로봇시스템학회:학술대회논문집
    • /
    • 제어로봇시스템학회 2001년도 ICCAS
    • /
    • pp.166.1-166
    • /
    • 2001
  • Anti-lock Braking System(ABS) is a device which prevents the wheels form locked up under emergency braking of a vehicle. So it helps the vehicle to maintain the steerability and shortens the braking distance by maintaining optimal frictional force during braking since the tire road slip is controlled in acceptable range. Recently, ABS is accepted as a standard equipment in vehicles, especially in commercial vehicles(bus and trucks). Commercial vehicles don´t use hydraulic lines but use pneumatic lines for braking system mostly. In this paper, ECU(Electronic Control Unit) for the anti-lock braking system of a commercial vehicle which is equipped with a full-air brake system and its control algorithms are presented. In this algorithm wheel speed acceleration flags and wheel slip flags are defined ...

  • PDF

전 차륜 조향 시스템 전자 제어 장치의 스윙 아웃 억제 알고리즘 개선에 대한 연구 (A Study of an Improvement of Swing-out Suppression Algorithm of an All Wheel Steering Electronic Control Unit)

  • 이효걸;정기현;최경희
    • 한국자동차공학회논문집
    • /
    • 제21권5호
    • /
    • pp.25-33
    • /
    • 2013
  • All-wheel steering (AWS) system is applied to articulated vehicles to reduce turning radius. The swing-out suppression algorithm is applied to AWS ECU, a key component of AWS system. The swing-out suppression algorithm applied to AWS ECU has a problem when velocity of vehicle is changed. In this paper, new algorithm based on moving distance that solve velocity problem is proposed. The HILS simulation and the test articulated bus is used to validate algorithm.

Low-Voltage-Stress AC-Linked Charge Equalizing System for Series-Connected VRLA Battery Strings

  • Karnjanapiboon, Charnyut;Jirasereeamornkul, Kamon;Monyakul, Veerapol
    • Journal of Power Electronics
    • /
    • 제13권2호
    • /
    • pp.186-196
    • /
    • 2013
  • This paper presents a low voltage-stress AC-linked charge equalizing system for balancing the energy in a serially connected, valve-regulated lead acid battery string using a modular converter that consists of multiple transformers coupled together. Each converter was coupled through an AC-linked bus to increase the overall energy transfer efficiency of the system and to eliminate the problem of the unbalanced charging of batteries. Previous solutions are based on centralized and modularized topologies. A centralized topology requires a redesign of the hardware and related components. It also faces a high voltage stress when the number of batteries is expanded. Modularized solutions use low-voltage-stress, double-stage, DC-linked topologies which leads to poor energy transfer efficiency. The proposed solution uses a low-voltage stress, AC-linked, modularized topology that makes adding more batteries easier. It also has a better energy transfer efficiency. To ensure that the charge equalization system operates smoothly and safely charges batteries, a small intelligent microcontroller was used in the control section. The efficiency of this charge equalization system is 85%, which is 21% better than other low-voltage-stress DC-linked charging techniques. The validity of this approach was confirmed by experimental results.

A Multithreaded Implementation of HEVC Intra Prediction Algorithm for a Photovoltaic Monitoring System

  • Choi, Yung-Ho;Ahn, Hyung-Keun
    • Transactions on Electrical and Electronic Materials
    • /
    • 제13권5호
    • /
    • pp.256-261
    • /
    • 2012
  • Recently, many photovoltaic systems (PV systems) including solar parks and PV farms have been built to prepare for the post fossil fuel era. To investigate the degradation process of the PV systems and thus, efficiently operate PV systems, there is a need to visually monitor PV systems in the range of infrared ray through the Internet. For efficient visual monitoring, this paper explores a multithreaded implementation of a recently developed HEVC standard whose compression efficiency is almost two times higher than H.264. For an efficient parallel implementation under a meshbased 64 multicore system, this work takes into account various design choices which can solve potential problems of a two-dimensional interconnects-based 64 multicore system. These problems may have not occurred in a small-scale multicore system based on a simple bus network. Through extensive evaluation, this paper shows that, for an efficient multithreaded implementation of HEVC intra prediction in a mesh-based multicore system, much effort needs to be made to optimize communications among processing cores. Thus, this work provides three design choices regarding communications, i.e., main thread core location, cache home policy, and maximum coding unit size. These design choices are shown to improve the overall parallel performance of the HEVC intra prediction algorithm by up to 42%, achieving a 7 times higher speed-up.