• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.56-65
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• 2009

As increasing the number of IPs integrated in a single chip and requiring high communication bandwidth on a chip, the trend of SoC communication architecture is changed from bus- or crossbar-based architecture to packet switched network architecture, NoC. However, highly complex control logics in routers require multiple cycles to switch packet. In this paper, we design low complex router to improve the communication latency. Our NoC design is verified by simulation platform modeled by ESL tool, SoC Designer. We also evaluate our NoC design comparing to the previous NoC architecture based on VC router. Our results show that our NoC architecture has less communication latency, even small throughput degradation (about 1-2%).

• 제어로봇시스템학회:학술대회논문집
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• 1987.10a
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• pp.770-775
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• 1987

In this paper, design and development experiences of a vision based robotic assembly system for electronic components are described. Specifically, the overall system consists of the following three subsystems each of which employs a 16 bit Preprocessor MC 68000 : supervisory controller, real-time vision system, and servo system. The three microprocessors are interconnected using the time shared common memory bus structure with hardwired bus arbitration scheme and operated as a master-slave type in which each slave is functionally fixed in view of software. With this system architecture, the followings are developed and implemented in this research; (i) the system programming language, called 'CLRC', for man-machine interface including the robot motion and vision primitives, (ii) real-time vision system using hardwired chain coder, (iii) the high-precision servo techniques for high speed de motors and high speed stepping motors. The proposed control system were implemented and tested in real-time successfully.

• Proceedings of the KSME Conference
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• 2000.04a
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• pp.884-889
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• 2000

This paper describes the design and implementation of PCOAMC(PC-based Open Architecture Machine Controller) to be flexible and independent from the vendor-oriented hardware and software structure. This openness approach is able to enhance an intelligence and integration of a manufacturing system. The development methodology of PcOAMC is an Object-Oriented approach, and all modules in PcOAMC are modelled using UML(Unified Modelling Language) that provides an easy understanding and modification. In order to demonstrate an applicability of PcOAMC, a simple test has been executed by using the Client-Server system consisting of two PcOAMCS and bus monitoring system. The good results have been obtained, so that the developed controller is expected to be embedded into IMS(Intelligent Manufacturing System) as a basic unit.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.2
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• pp.38-44
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• 2003

In this paper, we propose the method in which multimedia data simultaneously transfers to the main memory and the multimedia processor from the network interface card to improve bottleneck of system bus through analysis for architecture of video conference system and input/output model. The proposed method can reduce the number of system bus accesses, bus cycles, data transmission time and compression ratio of video data in the video conference system. We compared the performance between the proposed method and the conventional methods in the multi-party video conference systems. The simulation results showed that the proposed method was reduced the transmission time of multimedia data than the conventional method.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.10
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• pp.940-947
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• 2007

For the performance upgrade of a supersonic jet fighter, the processor and FLCC(Flight Control Computer) Architecture were upgraded from a baseline FLCC. Prior to the hardware implementation phase, the exact CPU throughput estimation is necessary. For this purpose, an experimental method for new FLCC throughput estimation was introduced in this study.　While baseline FLCC operating, the CPU address bus was collected with logic analyzer, and then decoded to get the exact access times to each memory-memory and the number of program Instruction branches. Based on these data, a throughput test in CPU demo-board of the new FLCC configuration was performed. From test results, the CPU-Memory architecture was design-changed before FLCC hardware implementation phase. To check the flight stability degradation due to power-interrupt problem due to CPU-Memory architecture change, the piloted HILS (Hardware-In-the Loop Simulator) test was conducted.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.9
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• pp.503-513
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• 2002

Since CC-NUMA architecture has to access remote memory, the interconnection network determines the performance of the CC-NUMA system. Bus which has been used as a popular interconnection network has many limits in a large-scale system because of the limited physical scalability and bandwidth. The dual ring interconnection network, composed of high-speed point-to-point links, is made to resolve the defects of the bus for the large-scale system. However, it also has a problem, in that the response latency is rapidly increased when many nodes are attached to the snooping based CC-NUMA system with the dual ring. In this paper, we propose a ring architecture with repeater nodes in order to overcome the problem of the dual ring on a snooping based CC-NUMA system, and design a repeater node adapted to this architecture. We will also analyze the effects of proposed architecture on the system performance and the response latency by using a probability-driven simulator.

• Journal of the Korean Institute of Rural Architecture
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• v.11 no.3
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• pp.11-18
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• 2009

The purpose of this paper is to find out the investigation of overseas case in Street Furnitures of Public Design. Thus this research regions select among the waterfront cities; Tokyo/Yokohama(Japan), Nies/Cannes(France), Shanghai(China), Vancouver(Canada), in addition to the city of art and romance; Paris. Above all, it is necessary to study concept of public design and definition of street furnitures. The survey data collected from forenamed cities and the items of street furnitures are various installments such as kiosk, bench, bollard, litter-bin, sign board, toilet, bus/taxi station, fence, shelter, lighting column, fountain, telephone-booth, clock-tower, automaton, bicycle stand, playing object etc. In this study street spaces are analysed that is related to regional surroundings and pedestrian's culture. Consequently, design trend of street furniture in foreign case analysis are going into thoroughly modern image as well as checking of form, color, material and maintenance system. According to the above findings, this paper will provide basic data for establishing of the street furniture and improving of public design to the regional citizen, local government officials and regional experts.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.68-75
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• 2016

As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.286-288
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• 2003

본 논문에서는 서로 다른 네트워크간의 다양한 프로토콜과 이종의 트래픽을 동시에 처리할 수 있는 네트워크용 SoC (System-on-a-Chip) 프로세서를 구현하였다. 제작된 네트워크 SoC 프로세서는 ARM 프로세서 코어와 ATM(Asynchronous Transfer Mode) 블록, 10/100 Mbps 이더넷 볼록, 스케쥴러, UART 등을 이용하였고 각 블록은 AM8A (Advanced Microcontroller Bus Architecture) 버스로 연결하였다. SoC 프로세서는 CADENCE사의 VerilogHDL을 이용하여 설계하였고 0.35$\mu\textrm{m}$ 셀 라이브러리를 이용하여 검증하였다. 구현된 칩은 총 게이트수가 312,000개이며 칠의 최대 동작 주파수는 50MHz 이다.

• Journal of the Korea Safety Management & Science
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• v.17 no.1
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• pp.33-43
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• 2015

Modern systems development becomes more and more complicated due to the need on the ever-increasing capability of the systems. In addition to the complexity issue, safety concern is also increasing since the malfunctions of the systems under development may result in the accidents in both the test and evaluation phase and the operation phase. Light rail transit(LRT) with passenger capacity between bus and subway is driven by an unmanned control, so safety issues of LRT in emergency shall be considered more carefully than other rolling stock. Modern railway system is a complex system and many actions in emergency are required. In this view, interoperability approach is effective to identify the related elements in emergency. In this paper, we propose the method to generate the fire response scenario of unmann ed LRT based on the outputs of systems engineering architecture design methodology. The proposed method is could be contributed to establish more reliable and applicable fire response scenario.