• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.6
• /
• pp.48-55
• /
• 1998

In this work, the testable CAM(Content Addressable Memory) is designed to perform the test effectively by inserting the ECC(Error Checking Circuit) inside the CAM. The designed CAM has the circuit which is capable of testing the functional faults in read, write, and match operations. In general the test circuit inserted causes the increase of total circuit area, Thus this work, utilizes the new MTA code to reduce the overhead of an area of the built-in test circuit which has a conventional parallel comparator. The designed circuit was verified using the VHDL simulator and the layout was performed using the 0.8${\mu}{\textrm}{m}$ double metal CMOS process. About 30% reduction of a circuit area wad achieved in the proposed CAM using the XOR circuit

• Proceedings of the Korea Information Processing Society Conference
• /
• 2002.04a
• /
• pp.635-638
• /
• 2002

BIST(Built-In Self-Test)를 이용한 테스트 방식은 정상 동작 모드인 회로에 비해 테스트 모드에서 보다 많은 스위칭이 발생하고, 과도한 전력 소모에 의해 회로가 손상을 받을 수 있는 문제점을 갖고 있다. 본 논문은 test-per-clock BIST 구조에서 전력이 제한되어 있을 때 테스트 적용 시간과 총 에너지 소비를 최소화하기 위한 테스트 스케줄링 알고리즘을 제안한다. 제안된 방법은 테스트 세션을 구성함에 있어 각 세션에 포함되는 각 블록의 테스트 시작 시간을 동적으로 결정하여 기존의 알고리즘에 비하여 전력 소모와 전체 테스트 시간을 줄일 수 있다.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.9
• /
• pp.2378-2387
• /
• 1998

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2001.10b
• /
• pp.1459-1462
• /
• 2001

혼성 신호 회로의 설계에 있어 저비용의 고효율 테스트 효율을 보장하기 위해 테스트의 노력은 계속되어 왔다. 특히 테스트를 고려한 BIST(built-in-self-test)설계 방법으로 발전해가고 있는 추세인데, 회로상에서 전체적인 테스트 용이도와 분석에 있어 보다 향상된 방법으로 접근할 수 있고 이러한 시스템에 대해 분석하는데 수월하게 할 수도 있다. 이 논문에서는 효과적인 테스트를 위한 방법을 위해 전압 검출기를 이용한 기준 전압 DC 테스트로써 테스트시간을 감소시키고 효과적인 고장 검출률을 갖는 BIST를 구현하는 것을 제안하였다. 즉 정상적인 회로와 고장회로에서의 동작에서 전압의 파이를 검출하는 회로를 하드웨어상으로 구성함으로써 비용과 시간등을 효과적으로 줄이는 방법을 제안하였다. 실험 결과에서는 기존의 BIST와 비교하여 향상된 것을 나타낸다.

• Journal of Advanced Technology Convergence
• /
• v.2 no.3
• /
• pp.9-15
• /
• 2023

Recently, various public services are being performed based on information systems as the informatization business spreads. Public administration services based on these information systems provide internal and external services. In recent years, as the construction of cloud-based public services has been expanded, the advancement of information systems has attracted attention. In particular, as the dependence on information systems increases, the establishment of a response system to prevent dangerous situations such as interruption and paralysis of information systems in advance has become a hot topic not only in companies but also in public institutions. Therefore, in this paper, a disaster recovery system was designed and built to maximize the efficiency of system operation and shorten recovery time through service conversion automation of the disaster recovery system. The integrated DR server redundancy test, web server redundancy test, FC-IP redundancy test, and SAN switch redundancy test were performed respectively by applying the disaster recovery system designed and built according to the method proposed in the paper.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.7
• /
• pp.81-88
• /
• 2002

A new pattern generator of BIST based on the pattern clustering is developed. The proposed technique embeds a pre-computed deterministic test set with low hardware overhead for test-per-clock environments. The test control logic is simple and can be synthesized automatically. Experimental results for the ISCAS benchmark circuits show that the effectiveness of the new pattern generator compared to the previous methods.

• Journal of KIISE:Software and Applications
• /
• v.32 no.7
• /
• pp.592-600
• /
• 2005

Systematically extracting the test patterns of hot spots in an object-oriented software framework is a prerequisite for thoroughly testing the framework's functionality in a variety of contexts in which the framework is extended for reuse. This paper proposes a method for analyzing the design patterns and extracting the test patterns from the interaction test patterns of hot spots in an object-oriented framework. Based on the design pattern of the framework's hot spot, our method captures the object behavior allowed in that hot spot by means of statecharts, which are then used to generate the interaction test patterns and test cases. The generated test patterns and test cases can be applied repeatedly to applications which are built from extending the framework.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.1069-1072
• /
• 1998

Recently the development of design and automation technology and manufacturing method, has reduced the cost of chip, but it becomes more difficult to test IC chip because test technique doesn't keep up with these techniques. In case of IC testing, obtaining test vectors to be able to detect good chip or bad one is very important, but according to increasing complexity, it is very complex and difficult. Another problem is that during testing, there could be capability of physical and electrical damage on chip. Also there is difficulty in synchronization between CUT (circuit under test) and Test equipment〔1〕. Because of these difficulties, built in self test has been proposed. Not only obtaining test vectors but also reducing test time becomes hot issues nowadays. This paper presents a new test BIST(built in self test) method. Proposed BIST implementation reduces test time and obtains high fault coverage. By searching internal nodes in which are inserted test_point_cells〔2〕and allocating TPG(test pattern generation) stages, test length becomes much shorter.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.8
• /
• pp.10-22
• /
• 1998

To handle the density increase of SRAMs, a new parallel testing methodology based on built-in self test (BIST) is developed, which allows to access multiple cells simultaneously. The main idea is that a march algorithm is dperformed concurently in each baisc marching block hwich makes up whole memory cell array. The new parallel access method is very efficient in speed and reuqires a very thny hardware overhead for BIST circuitry. Results show that the fault coverage of the applied march algorithm can be achieved with a lower complexity order. This new paralle testing algorithm tests an .root.n *.root.n SRAM which consists of .root.k * .root.k basic marching blocks in O(5*.root.k*(.root.k+.root.k)) test sequence.

• Proceedings of the KSR Conference
• /
• 2010.06a
• /
• pp.2223-2231
• /
• 2010

Recently, an important physical device of transportation, such as car, railroad, ship and aircraft has changed into electronic control unit. According to accident reports, the most of car accidents are caused by faults of embedded software loaded to computer control unit. The facts implies that the test to find defects in embedded software haven't performed sufficiently. As a result, it is necessary to establish the test procedures of embedded software based on safety assessment criteria. The objective of this proposal is to provide a unit test procedure complied with the safety assessment criteria for the embedded software. In addition, an effective unit testing procedure and defect analysis methods are proposed and a testing procedure using a safety criteria built-in tool is presented.