• Journal of Welding and Joining
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• 제19권2호
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• pp.98-103
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• 2001

Root gap out of standard by welding deformation is frequently produced at butt weld joints of steel bridge. For example although standard root gap is below 6mm at butt weld joints of plates under 15mm thickness. maximum 35mm root opening is produced at the weld field. At this case, the part out of standard is generally built up and the rest part is welded by WPS. Direct welding without built-up welding is preferred in weld field because built-up welding process bring about the cost-up at manufacturing. To apply this direct weld to root gap out of standard, the investigation about mechanical properties and fatigue at weldment is required. Inthisstudy, therefore the verification for direct weld without built up is performed at weldment as root gap. It includes tension, bending. hardness, impact and fatigue test for each welding specimen of 6mm, 25mm, 35mm root gap.

• 한국지반공학회논문집
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• 제31권3호
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• pp.5-16
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• 2015

본 연구에서는 토사 또는 암반 틈새에 주입하는 그라우팅(시멘트 페이스트)에 섬유를 혼합할 경우 발생하는 인장강도의 특성을 연구하였다. 이와 같이 시멘트로 고결된 토목재료의 인장강도 평가에는 간접적인 방법으로 인장강도를 평가하는 쪼갬인장시험을 주로 사용하고 있다. 하지만, 본 연구에서는 강섬유 또는 PVA 섬유를 중량비로 0%, 0.5%, 또는 1% 혼합한 시멘트 페이스트 내에 유압 실린더를 내장한 직경 15cm, 높이 30cm의 공시체를 제작한 다음 공시체 내부에서 직접 인장력을 가하는 직접인장시험법을 개발하였다. 또한 동일한 재료로 직경 5cm, 높이 10cm 공시체를 만들어 쪼갬인장시험을 실시하여 인장강도 시험방법에 따른 시멘트 페이스트의 인장강도를 비교, 평가하였다. 각각의 공시체는 대기 중에서 7일 또는 28일 양생한 다음 인장시험을 실시하였다. 시험방법에 따른 인장강도는 내장형 실린더를 이용한 직접인장시험법이 쪼갬인장시험법 보다 96%-290% 정도 높은 값을 보였다. 한편 두 종류의 인장시험법에 대한 3차원 유한요소해석을 실시하였으며, 실험 결과와 유사하게 내장형 실린더 인장시험법이 3배 정도 높은 인장강도를 보였다. 섬유 혼합량이 1%까지 증가함에 따라 인장강도는 시험방법에 관계없이 7일 양생한 공시체는 119%-190%, 28일 양생한 공시체는 23%-131%까지 증가하였으며, 양생일수가 7일에서 28일로 증가함에 따라 인장강도는 대부분 감소하는 경향을 보였다. 대부분의 경우 강섬유가 포함된 경우보다 PVA 섬유가 포함된 경우에 약 14%-38% 정도 높은 인장강도를 보였다.

• Steel and Composite Structures
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• 제34권3호
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• pp.377-391
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• 2020

A concrete filled steel tube (CFT) column with stiffeners has preferable behavior subjected to axial loading condition due to delay local buckling of the steel wall than traditional CFT columns without stiffeners. Welding lines in welded built-up steel box columns is expected to behave as longitudinal stiffeners. This study has presented a numerical investigation into the behavior of built-up concrete filled steel tube columns under axial pressure. At first stage, a finite element model (FE) has been built to simulate the behavior of built-up CFT columns. Comparing the results of FE and test has shown that numerical model passes the desired conditions and could accurately predict the axial performance of CFT column. Also, by the raise of steel tube thickness, the load bearing capacity of columns has been increased due to higher confinement effect. Also, the raise of concrete strength with greater cross section is led to a higher load bearing capacity compared to the steel tube thickness increment. In CFT columns with greater cross section, concrete strength has a higher influence on load bearing capacity which is noticeable in columns with more welding lines.

• 한국정보통신학회논문지
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• 제8권2호
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• pp.449-455
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• 2004

본 논문에서는 입력 정합(input matching) BIST(Built-In Self-Test, 자체내부검사) 회로를 이용한 RF front end(고주파 전단부)의 새로운 결함 검사방법을 제안한다. 자체내부검사 회로를 가진 고주파 전단부는 1.8GHz LNA(Low Noise Amplifier, 저 잡음 증폭기)와 이중 대칭 구조의 Gilbert 셀 믹서로 구성되어 있으며, TSMC 40.25{\mu}m$ CMOS 기술을 이용하여 설계되었다. catastrophic 결함(거폭 결함) 및 parametric 변동 (미세 결함)을 가진 고주파 전단부와 결함을 갖지 않은 고주파 전단부를 판별하기 위해 고주파 전단부의 입력 전압특성을 조사하였다. 본 검사방법에서는 DUT(Device Under Test, 검사대상이 되는 소자)와 자체내부검사회로가 동일한 칩 상에 설계되어 있기 때문에 측정할 때 단지 디지털 전압계와 고주파 전압 발생기만 필요하며, 측정이 간단하고 비용이 저렴하다는 장점이 있다.

• ETRI Journal
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• 제36권2호
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• pp.301-308
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• 2014

Three-dimensional integration technology results in area savings, platform power savings, and an increase in performance. Through-silicon via (TSV) assembly and manufacturing processes can potentially introduce defects. This may result in increases in manufacturing and test costs and will cause a yield problem. To improve the yield, spare TSVs can be included to repair defective TSVs. This paper proposes a new built-in self-test feature to identify defective TSV channels. For defective TSVs, this paper also introduces dynamic self-repair architectures using code-based and hardware-mapping based repair.

• 품질경영학회지
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• 제24권1호
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• pp.61-72
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• 1996

It is very important to determine the likelihood ratios and the prior odds for designing a Bayesian processor in Built-In-Test system. Using traditional statistics, it is not difficult to determine the initial prior odds from the field data. For a newly designed system, development testing data or laboratory testing data could be used to replace field data. The likelihood ratios which playa key role in the Bayesian processor must be carefully determined, based on laboratory testing and statistical techniques. In this paper, expressing and determining the likelihood ratios by Geometric areas, Test, and Analytical method will be presented.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.271-274
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• 2003

This paper presents a Built-in Current Sensor that detect defects in CMOS integrated circuits using the current testing technique. This scheme employs a cross-coupled connected PMOS transistors, it is used as a current comparator. Our proposed scheme is a negligible impart on the performance of the circuit undo. test (CUT). In addition, in the normal mode of the CUT not dissipation extra power, high speed detection time and applicable deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The entire area of the test chip is $116{\times}65{\mu}m^2$. The BICS occupies only $41{\times}17{\mu}m^2$ of area in the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS technology.

• 전자공학회논문지C
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• 제34C권8호
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• pp.49-63
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• 1997

This paper presents a current sensor that detects defects in CMOS integrated circuits using the current testing technique. The current sensor is built in a CMOS integrated circuit to test an abnormal current. The proposed circuit has a very small impact on the performance of the circuit under test during the normal mode. In the testing mode, the proposed circuit detects the abnormal current caused by permanent manufacturing defects and determines whether the circuit under test is defect-free or not. The proposed current sensor is simple and requires no external voltage and current sources. Hence, the circuit has less area and performance degradation, and is more efficient than any previous works. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects.

• ETRI Journal
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• 제26권6호
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• pp.520-534
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• 2004

As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권6호
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.