ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
권호 표지
DOI QR코드

DOI QR Code

Dynamic Self-Repair Architectures for Defective Through-silicon Vias

  • Yang, Joon-Sung (Department of Semiconductors System Engineering, Sungkyunkwan University) ;
  • Han, Tae Hee (Department of Semiconductors System Engineering, Sungkyunkwan University) ;
  • Kobla, Darshan (Intel Corporation) ;
  • Ju, Edward L. (Intel Corporation)
  • Received : 2013.06.11
  • Accepted : 2013.10.09
  • Published : 2014.04.01
Download PDF
⟨ Previous Next ⟩

Abstract

Three-dimensional integration technology results in area savings, platform power savings, and an increase in performance. Through-silicon via (TSV) assembly and manufacturing processes can potentially introduce defects. This may result in increases in manufacturing and test costs and will cause a yield problem. To improve the yield, spare TSVs can be included to repair defective TSVs. This paper proposes a new built-in self-test feature to identify defective TSV channels. For defective TSVs, this paper also introduces dynamic self-repair architectures using code-based and hardware-mapping based repair.

Keywords

References

  1. T.-C. Huang, "High-Performance Built-in Self-Routing for Through-Silicon Vias," Electron. Lett., vol. 48, no. 9, Apr. 2012, pp. 480-482. https://doi.org/10.1049/el.2012.0286
  2. H.-Y. Huang, Y.-S. Huang, and C.-L. Hsu, "Built-in Self-Test/Repair Scheme for TSV-Based Three-Dimensional Integrated Circuits," Proc. IEEE Asia Pacific Conf. Circuits Sys. (APCCAS), Kuala Lumpur, Malaysia, Dec. 6-9, 2010, pp. 56-59.
  3. U. Kang et al., "8 Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology," IEEE J. Solid-State Circuits, vol. 45, no. 1, Jan. 2010, pp. 111-119. https://doi.org/10.1109/JSSC.2009.2034408
  4. L. Jiang, R. Ye, and Q. Xu, "Yield Enhancement for 3D-Stacked Memory by Redundancy Sharing Across Dies," Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD), San Jose, CA, USA, Nov. 7-11, 2010, pp. 230-234.
  5. L. Jiang et al., "Modeling TSV Open Defects in 3D-Stacked DRAM," Proc. IEEE Int. Test Conf. (ITC), Austin, TX, USA, Nov. 2-4, 2010, pp. 1-9.
  6. L. Jiang, Q. Xu, and B. Eklow, "On Effective TSV Repair for 3D-Stacked ICs," Proc. Conf. Exhibition (DATE), Dresden, Germany, Mar. 12-16, 2012, pp. 793-798.
  7. D. Velenis, E.J. Marinissen, and E. Beyne, "Cost Effectiveness of 3D Integration Options," Proc. IEEE Int. 3D Sys. Integr. Conf. (3DIC), Munich, Germany, Nov. 16-18, 2010, pp. 1-6.
  8. M. Kawano et al., "Three-Dimensional Packaging Technology for Stacked DRAM with 3-Gb/s Data Transfer," IEEE Trans. Electron Devices, vol. 55, no. 7, July 2008, pp. 1614-1620. https://doi.org/10.1109/TED.2008.924068
  9. R.S. Patti, "Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs," Proc. IEEE, vol. 94, no. 6, June 2006, pp. 1214-1224. https://doi.org/10.1109/JPROC.2006.873612
  10. L. Yu et al., "Methodology for Analysis of TSV Stress Induced Transistor Variation and Circuit Performance," Proc. Int. Symp. Quality Electron. Des. (ISQED), Santa Clara, CA, USA, Mar. 19-21, 2012, pp. 216-222.
  11. M. Pathak et al., "Electromigration Modeling and Full-Chip Reliability Analysis for BEOL Interconnect in TSV-Based 3D ICs," Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD), San Jose, CA, USA, Nov. 2011, pp. 555-562.
  12. Q. Xu et al., "Yield Enhancement for 3D-Stacked ICs: Recent Advances and Challenges," Proc. Asia South Pacific Des. Automation Conf. (ASP-DAC), Sydney, NSW, Australia, Jan. 30 - Feb. 2, 2012, pp. 731-737.
  13. E.J. Marinissen and Y. Zorian, "Testing 3D Chips Containing Through-Silicon Vias," Proc. IEEE Int. Test Conf. (ITC), Austin, TX, USA, Nov. 1-6, 2009, pp. 1-11.
  14. A.P. Karmarkar, X. Xu, and V. Moroz, "Performance and Reliability Analysis of 3D-Integration Structures Employing Through Silicon Via (TSV)," Proc. IEEE Int. Rel. Physics Symp., Montreal, QC, Canada, Apr. 26-30, 2009, pp. 682-687.
  15. M. Jung et al., "TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3D IC," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 31, no. 8, Aug. 2012, pp. 1194-1207. https://doi.org/10.1109/TCAD.2012.2188400
  16. J.-S. Yang et al., "Robust Clock Tree Synthesis with Timing Yield Optimization for 3D-ICs," Proc. Asia South Pacific Des. Automation Conf. (ASP-DAC), Yokohama, Japan, Jan. 25-28, 2011, pp. 621-626.
  17. A. Dutta and N.A. Touba, "Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code," Proc. IEEE VLSI Test Symp. (VTS), Berkeley, CA, USA, May 6-10, 2007, pp. 349-354.