• Journal of Communications and Networks
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• v.16 no.6
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• pp.656-666
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• 2014

In delay tolerant networks (DTNs), delay is inevitable; thus, making better use of buffer space to maximize the packet delivery rate is more important than delay reduction. In DTNs, epidemic routing is a well-known routing protocol. However, epidemic routing is very sensitive to buffer size. Once the buffer size in nodes is insufficient, the performance of epidemic routing will be drastically reduced. In this paper, we propose a buffer scheme to optimize the performance of epidemic routing on the basis of the Lagrangian and dual problem models. By using the proposed optimal buffer scheme, the packet delivery rate in epidemic routing is considerably improved. Our simulation results show that epidemic routing with the proposed optimal buffer scheme outperforms the original epidemic routing in terms of packet delivery rate and average end-to-end delay. It is worth noting that the improved epidemic routing needs much less buffer size compared to that of the original epidemic routing for ensuring the same packet delivery rate. In particular, even though the buffer size is very small (e.g., 50), the packet delivery rate in epidemic routing with the proposed optimal buffer scheme is still 95.8%, which can satisfy general communication demand.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.23-32
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• 1996

This paper proposes a new buffer management scheme to service delay-sensitive traffic and loss-sensitive traffic fairly in ATM networks. The proposed scheme uses tow buffers for delay-sensitive traffic and loss-sensitive traffic. To satisfy the average delay time of delay-sensitive traffic, cells in real-time buffer are served first. When congestion occurs in nonreal-time buffer, low loss priority cell in real-time buffer can be pushed out by high loss priority cell in nonreal-time buffer can be transferred to real-time buffer considering threshold value in real-time buffer. Using computer simulation, the existing methods and proposed scheme are compared and analyzed with respect to cell loss rate and average delay time. Simulation results show that the proposed scheme have superior performance to conventional schemes.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.5
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• pp.509-521
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• 1988

In the designs of integrated circuits, the buffer circuits used for driving a large capacitive load from minimum-structured logic circuit outputs have important effects upon system throughputs. Therefore it is important to optimize the buffer circuits. In this paper, the principle of designing CMOS buffer circuits which have the minimum delay and drive the given capacitive load is discussed. That is, the effects of load capacitance upon rise time, fall time, and delay of the CMOS inverter and the effects of parasitic capacitances are finely analysed to calculate the requested minimum-delay CMOS buffer condition. This is different from the method by C.A. Mead et. al.[2.3.4.]which deals with passive-load-nMOS buffers. Large channel width MOS transistor stages are necessary to drive a large capacitive load. The effects of polysilicon gate resistances of such large stages upon delay are also analysed.And, the area of buffer circuits designed by the proposed method is smaller than that of buffer circuits designed by C.A. Mead's method.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1512-1515
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• 1987

The buffer circuit having minimum delay time is designed and analyzed in this paper. Considering the parasitic components of the MOS transistor, the optimal transistor size ratio between the individual buffer stages is presented. This paper's result is better than that of the Mead and Conway's analysis [1] with respect to both delay time and total area that buffer occupies.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.8
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• pp.3542-3566
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• 2018

In this paper, we investigate a buffer-aided wireless powered cooperative communication network (WPCCN), in which the source and relay harvest the energy from a dedicated power beacon via wireless energy transfer, then the source transmits the data to the destination through the relay. Both the source and relay are equipped with an energy buffer to store the harvested energy in the energy transfer stage. In addition, the relay is equipped with a data buffer and can temporarily store the received information. Considering the buffer-aided WPCCN, we propose two buffer-aided relaying protocols, which named as the buffer-aided harvest-then-transmit (HtT) protocol and the buffer-aided joint mode selection and power allocation (JMSPA) protocol, respectively. For the buffer-aided HtT protocol, the time-averaged achievable rate is obtained in closed form. For the buffer-aided JMSPA protocol, the optimal adaptive mode selection scheme and power allocation scheme, which jointly maximize the time-averaged throughput of system, are obtained by employing the Lyapunov optimization theory. Furthermore, we drive the theoretical bounds on the time-averaged achievable rate and time-averaged delay, then present the throughput-delay tradeoff achieved by the joint JMSPA protocol. Simulation results validate the throughput performance gain of the proposed buffer-aided relaying protocols and verify the theoretical analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.81-90
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• 2004

For deep submicron (DSM) very large scale integrated circuits (VLSI), it is well known that interconnects have become the dominant factor in determining the overall circuit performance. Buffer insertion is an effective technique of interconnect optimization. When a net has an excessive propagation delay, one or more buffers can be inserted to reduce the delay. Buffers also reduce the crosstalk between neighboring wires. While many conventional methods insert buffers net by net. we have developed new techniques in which buffer locations are simultaneously optimized for all nets. This is to avoid the difficulties in finding the right ordering of nets for buffer insertion. since several nets may compete for a buffer location. We also study buffer insertion with multiple fan-out nets to optimize critical path delay. Elmore delay model is used for delay calculation and the number of buffers for each net is determined to optimize the delay.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1996.06a
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• pp.153-158
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• 1996

Delay and jitter are critical factors in the real-time video services over ATM network. Mostly, delay and jitter problem are generated in input buffer when video are multiplexed. In this paper, we analyze delay and jitter of input buffer, and consider efficient control and flexible bandwidth allocation of video traffic. Also, we analyze decision of buffer size related maximum allowable delay.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.82.1-82
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• 2001

It is known that existence of irregular transmission time delay is a major bottleneck for application of advanced robot control schemes to internet telerobotic systems. In the internet teleoperation system, the irregular transmission time delay causes a critical problem, which is unstable and inaccurate. This paper suggests a practical internet teleoperation system with streaming buffer system, which consists of a buffer, a buffer manager, and a control timer. The proposed system converts the irregular transmission time delay to constant. So, the system effectively transmits the control input to a remote site to operate a robot stably and accurately. This feature enables short control input interval. That means the entire system has ...

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.4
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• pp.684-693
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• 2011

Measurement time delay in the transfer alignment is very important. It has been well known that the time delay degrades the alignment performance and makes some navigation errors on the transfer alignment of slave INS(SINS). Therefore there are many schemes to eliminate that time delay but the compensation technique through the estimation by Kalman filter through modeling the time delay as a random constant is generally used. In the case of change over measurement time delay or the large measurement time delay, estimation performance in the existing compensation technique is degraded because model of time delay is not correct any more. In this paper, we propose the method to keep the time delay almost constant even though in the abnormal communication state and very small through feedback compensation using double buffer. Double buffer consists of two moving window to temporarily store measurements from master INS and slave INS in real time.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.10
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• pp.95-102
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• 2003

The buffering is a promising solution to resolve the contention problem in optical network. we study the packet loss probability and the dimensioning of optical buffer using a Fiber Delay Line for variable length packet. In this paper, we study the relation between the granularity and the loss of FDL buffer in Single-Stage FDL buffer and propose the Single-Bundle Multi-Stage FDL buffer. The Multi-Stage FDL buffer is too early yet to apply to the current backbone network, considering the current technology in view of costs. but we assume that the above restriction will be resolved in these days. The appropriate number of delay and pass line for a dimensioning is based on a amount of occupied time by packets. Once more another multi-stage FDL buffer is proposed, Split-Bundle multi-stage FDL buffer. The Split-Bundle ms-FDL buffer is more feasible for a FDL buffer structure, considering not only a size of switching matrix but also a bulk of switching element. its feasibility will be demonstrated from a loss probability.