• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.4 s.304
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• pp.59-68
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• 2005

In this paper, we design a PCI Express controller for future communication system The controller supports the full functionality of Transaction Layer and Data Link Layer of PCI Express. The designed controller has the proposed transmitter buffer architecture to obey Replay mechanism. This scheme merges the transmitting buffer and the replay buffer. The proposed buffer has the higher data transfer efficiency than the conventional buffer architecture because it can dynamically adjust size of a replay buffer space. We also design transmitter of Transmitter Transaction Layer to effectively support the proposed buffer, The receiver device of PCI Express must possess the buffer for three types of transaction to support Flow Control. And it must report the amount of the buffer space regularly to the Port at the opposite end of the link. We propose the simple receiver buffer scheme using only one buffer to easily support Flow Control. And the designed controller is verified under proposed test bench

• Journal of the Korean Operations Research and Management Science Society
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• v.21 no.2
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• pp.17-33
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• 1996

Automatic transfer defined as an integrated system with a number of workstations, interstation storage buffers, automatic device and a control system, play a major role in ass production systems. Due to high capital investment needed for an automatic transferline, greater care should be taken in its design so as to maximize the system performance. One may to control the system performance is to control buffer storage. To control the interstation work-in-process inventory, we propose dual limit switches which control the buffer storage with two parameters, R and r. Under the policy, proceding station is forced down when the inventory level in the buffer reaches R until the level falls to r. For the model developed, we analyze the system characteristics and find the optimal control parameters with a serach procedure.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.243-246
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• 2002

This paper presents a study on the design and implementation of modulized I/O buffer control system for large capacity cable check. A 8bit I/O buffer basic module which has feedback loops with input and output buffers is simulated in PSpice and implemented with logic gates. This system is composed of 18 sub-boards which have 3 channels of 32bit data buses, and of a main board with MPC860 microprocessor.

• Journal of Families and Better Life
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• v.26 no.5
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• pp.91-107
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• 2008

This study investigated the isolation hypothesis and the buffer hypothesis of Demand-Control-Support model in relation to activity satisfaction and psychological well-being. The subjects were 300 elderly women participating in productive activity for example paid work, voluntary activity, and grancdhildren care. This research tested four hypotheses concerning the DCS model. Is there support for the isolation hypothesis, such that the lowest level of activity satisfaction is experienced by the elderly women working in an isolation situation(high demand-low control-low support)? Is there support for the isolation hypothesis, such that the lowest level of psychological well-being is experienced by the elderly women working in an isolation situation(high demand-low control-low support)? Is there support for the buffer hypothesis, i. e. interaction between demand, control, and support, indicating a buffering effect of support on the negative impact of high strain on activity satisfaction? Is there support for the buffer hypothesis, i. e. interaction between demand, control, and support, indicating a buffering effect of support on the negative impact of high strain on psychological well-being? Major results of this study were as follows. and were supported. Activity satisfaction and psychological well-being of the elderly women in isolation situation was the lowest among the sample. was supported that family support level buffered the negative impact of high strain on activity satisfaction. But was not supported. Only main effect of demand level was showed on psychological well-being.

• Journal of the Korea Computer Industry Society
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• v.3 no.9
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• pp.1251-1260
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• 2002

Real-time application programs have synchronization constraints which need to be met between media-data. Synchronization method represents feedback method including virtual client-side buffer. This buffer is used in buffer level method. It is client-leading synchronization that is absorbing variable transmission delay time and that is synchronizing by feedback control. It is the important factor for playback rate and QoS if the buffer level is normal or not. To solve the problems, we can control the start of transmission in multimedia server by appling filtering, control and network evaluation function. Synchronization method is processing for smooth presentation without cut-off while media is playing out. When audio frame which is master media is in high threshold buffer level we decrease play out time gradually, otherwise we increase it slowly.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.703-717
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• 2002

This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

• The KIPS Transactions:PartB
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• v.11B no.6
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• pp.625-632
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• 2004

Since the H.264 encoding adopts both forward prediction and hi-direction prediction modes and exploits Variable Length Coding(VLC), the amount of data generated from video encoder varies as Flaying time goes by. The fixed bit rate encoding system which has limited transmission channel capacity uses a buffer to control output bitstream It's necessary to control the bitstream to maintain within manageable range so as to protect buffer from overflow or underflow. With existing bit amount control algorithms, the $\lambda_{MODE}$ which is relationship between distortion value and quantization parameter often excesses normal value to end up with video error. This paper proposes an algorithm to protect buffer from overflow or underflow by introducing a new quantization parameter against distortion value of H.264 video data. The test results of 6 exemplary data show that the proposed algorithm has the same PSNR as and up to 8% reduced bit rate against existing algorithms.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.147-147
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• 2015

The multilayer structure of the organic light emitting diode has merits of improving interfacial characteristics and helping carriers inject into emission layer and transport easier. There are many reports to control hole injection from anode electrode by using transition metal oxide as an anode buffer layer, such as V2O5, MoO3, NiO, and Fe3O4. In this study, we apply thin films of LiF which is usually inserted as a thin buffer layer between electron transport layer(ETL) and cathode, as an anode buffer layer to reduce the hole injection barrier height from ITO. The thickness of LiF as an anode buffer layer is tested from 0 nm to 1.0 nm. As shown in the figure 1 and 2, the luminous efficiency versus current density is improved by LiF anode buffer layer, and the threshold voltage is reduced when LiF buffer layer is increased up to 0.6 nm then the device does not work when LiF thickness is close to 1.0 nm As a result, we can confirm that the thin layer of LiF, about 0.6 nm, as an anode buffer reduces the hole injection barrier height from ITO, and this results the improved luminous efficiency. This study shows that LiF can be used as an anode buffer layer for improved hole injection as well as cathode buffer layer.

• Culinary science and hospitality research
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• v.13 no.2
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• pp.254-259
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• 2007

The control of enzymic browning in potato slices by the use of citrate and phosphate buffer at different pH values and concentration was investigated. Minimally processed potatoes were stored at $5^{\circ}C$ and $20^{\circ}C$ followed by dipping in distilled water, citrate buffer (pH $3.0{\sim}5.0$) and phosphate buffer (pH $5.0{\sim}7.0$). The color characteristic was measured after storage at $5^{\circ}C$ and $20^{\circ}C$ for 24 hours. Treatment effectiveness was greatly improved by reducing pH and temperature. The citrate buffer was more effective than phosphate buffer in the browning inhibitory capacity. The citrate buffer (pH 3.0) showed the most anti-browning effect in this condition and more effective inhibition of browning by increasing concentration of treatment solution. The phosphate buffer (pH 5.0) treatment showed more effectiveness than concentration of 0.5 M of citrate buffer treatment.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.65-68
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• 2003

3GPP's RLC protocol specification adopted an error control scheme based on selective repeat ARQ. In 3GPP ARQ, distinctive windows are provide at transmitting and receiving stations so that those stations are prohibited to send or receive data PDU's out of window. An increase in window size enhances delay performance. Such an increase, however, raises the occupancy at reordering buffer, which results in a long reordering time. Aiming at suppressing the occupancy at reordering buffer, we propose a occupancy control scheme in this paper. In this scheme, a threshold is created in the receiving station's window and a data PDU out of the threshold (but within the window) is treated according to go back N ARQ. By the employment of the occupancy control scheme, the occupancy at the reordering buffer is apparently reduced, while the delay performance may be degraded due to the properties of go back N ARQ. We, thus, investigate the peak occupancy and mean delay performance by a simulation method. From numerical examples, we observe a trade-off in both performance measures and conclude that the peak occupancy is effectively reduced by setting a proper threshold under a constraint on mean delay performance.